1 files changed, 25 insertions, 15 deletions
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index d33355fd..f61fa36a 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -150,31 +150,41 @@ class BlackBoxWithParamsTester extends BasicTester {
 
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
-    assertTesterPasses({ new BlackBoxTester },
-        Seq("/chisel3/BlackBoxTest.v"))
+    assertTesterPasses(
+      {new BlackBoxTester},
+      Seq("/chisel3/BlackBoxTest.v"),
+      TesterDriver.verilatorOnly)
   }
   "A BlackBoxed with flipped IO" should "work" in {
-    assertTesterPasses({ new BlackBoxFlipTester },
-        Seq("/chisel3/BlackBoxTest.v"))
+    assertTesterPasses(
+      {new BlackBoxFlipTester},
+      Seq("/chisel3/BlackBoxTest.v"),
+      TesterDriver.verilatorOnly)
   }
   "Multiple BlackBoxes" should "work" in {
-    assertTesterPasses({ new MultiBlackBoxTester },
-        Seq("/chisel3/BlackBoxTest.v"))
+    assertTesterPasses(
+      {new MultiBlackBoxTester},
+      Seq("/chisel3/BlackBoxTest.v"),
+      TesterDriver.verilatorOnly)
   }
   "A BlackBoxed register" should "work" in {
-    assertTesterPasses({ new BlackBoxWithClockTester },
-        Seq("/chisel3/BlackBoxTest.v"))
+    assertTesterPasses(
+      {new BlackBoxWithClockTester},
+      Seq("/chisel3/BlackBoxTest.v"),
+      TesterDriver.verilatorOnly)
   }
   "BlackBoxes with parameters" should "work" in {
-    assertTesterPasses({ new BlackBoxWithParamsTester },
-        Seq("/chisel3/BlackBoxTest.v"))
+    assertTesterPasses(
+      {new BlackBoxWithParamsTester},
+      Seq("/chisel3/BlackBoxTest.v"),
+      TesterDriver.verilatorOnly)
   }
   "DataMirror.modulePorts" should "work with BlackBox" in {
     ChiselStage.elaborate(new Module {
-      val io = IO(new Bundle { })
-      val m = Module(new BlackBoxPassthrough)
-      assert(DataMirror.modulePorts(m) == Seq(
-          "in" -> m.io.in, "out" -> m.io.out))
-    })
+        val io = IO(new Bundle {})
+        val m = Module(new BlackBoxPassthrough)
+        assert(DataMirror.modulePorts(m) == Seq("in" -> m.io.in, "out" -> m.io.out))
+      }
+    )
   }
 }