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-rw-r--r--src/test/scala/chiselTests/AnalogSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index c78c8c0e..d81ed009 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
import chisel3._
import chisel3.util._
import chisel3.testers.BasicTester
-import chisel3.experimental.{Analog, attach, BaseModule, RawModule}
+import chisel3.experimental.{Analog, attach, BaseModule}
// IO for Modules that just connect bus to out
class AnalogReaderIO extends Bundle {