1 files changed, 7 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index 5db9ab53..c2dee4a9 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -130,7 +130,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mod = Module(new AnalogReaderBlackBox)
       mod.io.bus <> writer.io.bus
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "error if any bulk connected more than once" in {
@@ -149,7 +149,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox))
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with 3 blackboxes separately attached via a wire" in {
@@ -160,7 +160,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire, mods(0).io.bus)
       attach(mods(1).io.bus, busWire)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator unless Firrtl does constant prop and dead code
@@ -173,7 +173,7 @@ class AnalogSpec extends ChiselFlatSpec {
       attach(busWire(1), mod.io.bus)
       attach(busWire(0), busWire(1))
       check(mod)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "work with blackboxes at different levels of the module hierarchy" in {
@@ -182,7 +182,7 @@ class AnalogSpec extends ChiselFlatSpec {
       val busWire = Wire(writer.io.bus)
       attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
       mods.foreach(check(_))
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   // This does not currently work in Verilator, but does work in VCS
@@ -193,7 +193,7 @@ class AnalogSpec extends ChiselFlatSpec {
       connector.io.bus1 <> writer.io.bus
       reader.io.bus <> connector.io.bus2
       check(reader)
-    }, Seq("/AnalogBlackBox.v"))
+    }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 
   it should "NOT support conditional connection of analog types" in {
@@ -204,7 +204,7 @@ class AnalogSpec extends ChiselFlatSpec {
           mod.io.bus <> writer.io.bus
         }
         check(mod)
-      }, Seq("/AnalogBlackBox.v"))
+      }, Seq("/chisel3/AnalogBlackBox.v"))
     }
   }
 }