4 files changed, 8 insertions, 48 deletions
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index d5952834..02204684 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -46,17 +46,15 @@ trait BackendCompilationUtilities {
     * The Verilator prefix will be V$dutFile, and running this will generate
     * C++ sources and headers as well as a makefile to compile them.
     *
-    * Verilator will automatically locate the top-level module as the one among
-    * all the files which are not included elsewhere. If multiple ones exist,
-    * the compilation will fail.
-    *
     * @param dutFile name of the DUT .v without the .v extension
+    * @param name of the top-level module in the design
     * @param dir output directory
     * @param vSources list of additional Verilog sources to compile
     * @param cppHarness C++ testharness to compile/link against
     */
   def verilogToCpp(
       dutFile: String,
+      topModule: String,
       dir: File,
       vSources: Seq[File],
       cppHarness: File
@@ -70,8 +68,9 @@ trait BackendCompilationUtilities {
         "-Wno-STMTDLY",
         "--trace",
         "-O2",
+        "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
-        s"+define+PRINTF_COND=!$dutFile.reset",
+        s"+define+PRINTF_COND=!$topModule.reset",
         "-CFLAGS",
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
diff --git a/src/main/scala/Chisel/Tester.scala b/src/main/scala/Chisel/Tester.scala
deleted file mode 100644
index d02af842..00000000
--- a/src/main/scala/Chisel/Tester.scala
+++ /dev/null
@@ -1,39 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.util.Random
-
-class Tester[+T <: Module](c: T, isTrace: Boolean = true) {
-  def t: Int = 0
-  var ok: Boolean = true  // TODO: get rid of this
-
-  def rnd: Random = new Random()
-
-  def peek(data: Bits): BigInt = 0
-  def poke(data: Bits, x: BigInt): Unit = {}
-  def expect(data: Bits, expected: BigInt): Boolean = true
-  def step(n: Int): Unit = {}
-
-  // TODO: unify and disambiguate expect(...)
-  def expect(ok: Boolean, failureMsg: String): Boolean = true
-}
-
-object chiselMainOld {
-  val wrapped = true
-  val unwrapped = false
-
-  def apply[T <: Module](args: Array[String], gen: () => T): T = gen()
-
-  def apply[T <: Module](args: Array[String], gen: () => T, ftester: T => Tester[T]): T = gen()
-
-  // Assumes gen needs to be wrapped in Module()
-  def run[T <: Module] (args: Array[String], gen: () => T): T = gen()
-
-  def run[T <: Module] (args: Array[String], gen: () => T, ftester: T => Tester[T]): T = gen()
-}
-
-object chiselMainTest {
-  def apply[T <: Module](args: Array[String], gen: () => T)(tester: T => Tester[T]): T =
-    chiselMainOld(args, gen, tester)
-}
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index c0cdfb3f..a56bb8b7 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -47,7 +47,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
     if ((firrtlToVerilog(target, path) #&&
-        verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
         cppToExe(target, path)).! == 0) {
       executeExpectingSuccess(target, path)
     } else {
diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/Chisel/util/Reg.scala
index 44593dfd..6584a4bf 100644
--- a/src/main/scala/Chisel/util/Reg.scala
+++ b/src/main/scala/Chisel/util/Reg.scala
@@ -7,15 +7,15 @@ package Chisel
 
 object RegNext {
 
-  def apply[T <: Data](next: T): T = Reg[T](next, next, null.asInstanceOf[T])
+  def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T])
 
-  def apply[T <: Data](next: T, init: T): T = Reg[T](next, next, init)
+  def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init)
 
 }
 
 object RegInit {
 
-  def apply[T <: Data](init: T): T = Reg[T](init, null.asInstanceOf[T], init)
+  def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init)
 
 }