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-rw-r--r--src/main/scala/chisel3/compatibility.scala23
-rw-r--r--src/main/scala/chisel3/package.scala53
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala2
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala34
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala6
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala4
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala6
-rw-r--r--src/main/scala/chisel3/util/Counter.scala10
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala125
-rw-r--r--src/main/scala/chisel3/util/ImplicitConversions.scala2
-rw-r--r--src/main/scala/chisel3/util/OneHot.scala6
-rw-r--r--src/main/scala/chisel3/util/Reg.scala4
-rw-r--r--src/main/scala/chisel3/util/Valid.scala30
13 files changed, 168 insertions, 137 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index c0e933e0..b7020b5e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -5,11 +5,13 @@
package object Chisel {
type Direction = chisel3.core.Direction
- val INPUT = chisel3.core.INPUT
- val OUTPUT = chisel3.core.OUTPUT
- val NO_DIR = chisel3.core.NO_DIR
+ val INPUT = chisel3.core.Direction.Input
+ val OUTPUT = chisel3.core.Direction.Output
+ object Flipped {
+ def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
+ }
+ type ChiselException = chisel3.internal.ChiselException
- type Flipped = chisel3.core.Flipped
type Data = chisel3.core.Data
val Wire = chisel3.core.Wire
val Clock = chisel3.core.Clock
@@ -103,10 +105,13 @@ package object Chisel {
val Counter = chisel3.util.Counter
type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
- val Decoupled = chisel3.util.Decoupled
- type EnqIO[T <: Data] = chisel3.util.EnqIO[T]
- type DeqIO[T <: Data] = chisel3.util.DeqIO[T]
- type DecoupledIOC[+T <: Data] = chisel3.util.DecoupledIOC[T]
+ val DecoupledIO = chisel3.util.DecoupledIO
+ object EnqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+ }
+ object DeqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+ }
type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
type Queue[T <: Data] = chisel3.util.Queue[T]
val Queue = chisel3.util.Queue
@@ -133,7 +138,7 @@ package object Chisel {
val RegEnable = chisel3.util.RegEnable
val ShiftRegister = chisel3.util.ShiftRegister
- type ValidIO[+T <: Data] = chisel3.util.ValidIO[T]
+ type ValidIO[+T <: Data] = chisel3.util.Valid[T]
val Valid = chisel3.util.Valid
val Pipe = chisel3.util.Pipe
type Pipe[T <: Data] = chisel3.util.Pipe[T]
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 0b548683..9a79b109 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
package object chisel3 {
import scala.language.experimental.macros
@@ -7,10 +9,16 @@ package object chisel3 {
type Direction = chisel3.core.Direction
- val INPUT = chisel3.core.INPUT
- val OUTPUT = chisel3.core.OUTPUT
- val NO_DIR = chisel3.core.NO_DIR
- type Flipped = chisel3.core.Flipped
+ object Input {
+ def apply[T<:Data](target: T): T = chisel3.core.Input(target)
+ }
+ object Output {
+ def apply[T<:Data](target: T): T = chisel3.core.Output(target)
+ }
+ object Flipped {
+ def apply[T<:Data](target: T): T = chisel3.core.Flipped(target)
+ }
+
type Data = chisel3.core.Data
val Wire = chisel3.core.Wire
val Clock = chisel3.core.Clock
@@ -54,17 +62,40 @@ package object chisel3 {
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
+ /**
+ * These implicit classes allow one to convert scala.Int|scala.BigInt to
+ * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+ * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+ * mark a width for the new literal.
+ *
+ * Also provides .asBool to scala.Boolean and .asUInt to String
+ *
+ * Note that, for stylistic reasons, one should avoid extracting immediately
+ * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+ * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+ * Prefer storing the result and then extracting from it.
+ */
+ implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+ def U: UInt = UInt(BigInt(x), Width())
+ def S: SInt = SInt(BigInt(x), Width())
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
+ }
+
implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
def U: UInt = UInt(x, Width())
def S: SInt = SInt(x, Width())
- }
- implicit class fromIntToLiteral(val x: Int) extends AnyVal {
- def U: UInt = UInt(BigInt(x), Width())
- def S: SInt = SInt(BigInt(x), Width())
+
+ def asUInt() = UInt(x, Width())
+ def asSInt() = SInt(x, Width())
+ def asUInt(width: Int) = UInt(x, width)
+ def asSInt(width: Int) = SInt(x, width)
}
implicit class fromStringToLiteral(val x: String) extends AnyVal {
- def U: UInt = UInt(x)
+ def U: UInt = UInt.Lit(x)
}
implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
def B: Bool = Bool(x)
@@ -79,4 +110,8 @@ package object chisel3 {
def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
}
+
+ val INPUT = chisel3.core.Direction.Input
+ val OUTPUT = chisel3.core.Direction.Output
+ type ChiselException = chisel3.internal.ChiselException
}
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index f91536d5..329237c6 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -12,7 +12,7 @@ import internal.sourceinfo.SourceInfo
class BasicTester extends Module {
// The testbench has no IOs, rather it should communicate using printf, assert, and stop.
- val io = new Bundle()
+ val io = IO(new Bundle())
def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index eb541977..0ece3a0a 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -9,9 +9,9 @@ import chisel3._
/** An I/O bundle for the Arbiter */
class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
- val in = Vec(n, Decoupled(gen)).flip
- val out = Decoupled(gen)
- val chosen = UInt(OUTPUT, log2Up(n))
+ val in = Flipped(Vec(n, DecoupledIO(gen)))
+ val out = DecoupledIO(gen)
+ val chosen = Output(UInt.width(log2Up(n)))
}
/** Arbiter Control determining which producer has access */
@@ -27,7 +27,7 @@ private object ArbiterCtrl
abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
def grant: Seq[Bool]
def choice: UInt
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
io.chosen := choice
io.out.valid := io.in(io.chosen).valid
@@ -36,17 +36,17 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
if (count > 1) {
val lockCount = Counter(count)
val lockIdx = Reg(UInt())
- val locked = lockCount.value =/= UInt(0)
+ val locked = lockCount.value =/= UInt.Lit(0)
val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
- when (io.out.fire() && wantsLock) {
+ when (io.out.firing && wantsLock) {
lockIdx := io.chosen
lockCount.inc()
}
when (locked) { io.chosen := lockIdx }
for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
- in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+ in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready
} else {
for ((in, g) <- io.in zip grant)
in.ready := g && io.out.ready
@@ -55,8 +55,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
extends LockingArbiterLike[T](gen, n, count, needsLock) {
- lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
- lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+ lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
+ lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant)
lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
override def grant: Seq[Bool] = {
@@ -64,20 +64,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
(0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
}
- override lazy val choice = Wire(init=UInt(n-1))
+ override lazy val choice = Wire(init=UInt.Lit(n-1))
for (i <- n-2 to 0 by -1)
- when (io.in(i).valid) { choice := UInt(i) }
+ when (io.in(i).valid) { choice := UInt.Lit(i) }
for (i <- n-1 to 1 by -1)
- when (validMask(i)) { choice := UInt(i) }
+ when (validMask(i)) { choice := UInt.Lit(i) }
}
class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
extends LockingArbiterLike[T](gen, n, count, needsLock) {
def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
- override lazy val choice = Wire(init=UInt(n-1))
+ override lazy val choice = Wire(init=UInt.Lit(n-1))
for (i <- n-2 to 0 by -1)
- when (io.in(i).valid) { choice := UInt(i) }
+ when (io.in(i).valid) { choice := UInt.Lit(i) }
}
/** Hardware module that is used to sequence n producers into 1 consumer.
@@ -101,13 +101,13 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
consumer.io.in <> arb.io.out
*/
class Arbiter[T <: Data](gen: T, n: Int) extends Module {
- val io = new ArbiterIO(gen, n)
+ val io = IO(new ArbiterIO(gen, n))
- io.chosen := UInt(n-1)
+ io.chosen := UInt.Lit(n-1)
io.out.bits := io.in(n-1).bits
for (i <- n-2 to 0 by -1) {
when (io.in(i).valid) {
- io.chosen := UInt(i)
+ io.chosen := UInt.Lit(i)
io.out.bits := io.in(i).bits
}
}
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index d476f957..5b37bd1b 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -68,7 +68,7 @@ object BitPat {
*/
def apply(x: UInt): BitPat = {
require(x.isLit)
- val len = if (x.width.known) x.getWidth else 0
+ val len = if (x.widthKnown) x.getWidth else 0
apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
}
}
@@ -76,7 +76,7 @@ object BitPat {
// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
/** Bit patterns are literals with masks, used to represent values with don't
* cares. Equality comparisons will ignore don't care bits (for example,
- * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
+ * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
*/
sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def getWidth: Int = width
@@ -84,7 +84,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
- def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value, width) === (that & UInt(mask))
+ def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt)
def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
}
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 3134d043..2743e59f 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -27,9 +27,9 @@ object Fill {
/** Fan out x n times */
def apply(n: Int, x: UInt): UInt = {
n match {
- case 0 => UInt(width=0)
+ case 0 => UInt.width(0)
case 1 => x
- case _ if x.width.known && x.getWidth == 1 =>
+ case _ if x.widthKnown && x.getWidth == 1 =>
Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
case _ if n > 1 =>
val p2 = Array.ofDim[UInt](log2Up(n + 1))
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index a64447d9..27bd7bfb 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,17 +10,17 @@ import chisel3._
/** Compute the base-2 integer logarithm of a UInt
* @example
* {{{ data_out := Log2(data_in) }}}
- * @note The result is truncated, so e.g. Log2(UInt(13)) = 3
+ * @note The result is truncated, so e.g. Log2(13.U) = 3
*/
object Log2 {
/** Compute the Log2 on the least significant n bits of x */
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
- UInt(0)
+ UInt.Lit(0)
} else if (width == 2) {
x(1)
} else if (width <= divideAndConquerThreshold) {
- Mux(x(width-1), UInt(width-1), apply(x, width-1))
+ Mux(x(width-1), UInt.Lit(width-1), apply(x, width-1))
} else {
val mid = 1 << (log2Ceil(width) - 1)
val hi = x(width-1, mid)
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 40615769..05d8fba8 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -10,17 +10,17 @@ import chisel3._
*/
class Counter(val n: Int) {
require(n >= 0)
- val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+ val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0)
/** Increment the counter, returning whether the counter currently is at the
* maximum and will wrap. The incremented value is registered and will be
* visible on the next cycle.
*/
def inc(): Bool = {
if (n > 1) {
- val wrap = value === UInt(n-1)
- value := value + UInt(1)
+ val wrap = value === UInt.Lit(n-1)
+ value := value + UInt.Lit(1)
if (!isPow2(n)) {
- when (wrap) { value := UInt(0) }
+ when (wrap) { value := UInt.Lit(0) }
}
wrap
} else {
@@ -33,7 +33,7 @@ class Counter(val n: Int) {
* Example Usage:
* {{{ val countOn = Bool(true) // increment counter every clock cycle
* val myCounter = Counter(countOn, n)
- * when ( myCounter.value === UInt(3) ) { ... } }}}*/
+ * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/
object Counter
{
def apply(n: Int): Counter = new Counter(n)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index f37a5c31..76bf4842 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -10,71 +10,64 @@ import chisel3._
/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
class DecoupledIO[+T <: Data](gen: T) extends Bundle
{
- val ready = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val bits = gen.cloneType.asOutput
- def fire(dummy: Int = 0): Bool = ready && valid
- override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type]
+ val ready = Input(Bool())
+ val valid = Output(Bool())
+ val bits = Output(gen.chiselCloneType)
+ override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
}
-/** Adds a ready-valid handshaking protocol to any interface.
- * The standard used is that the consumer uses the flipped interface.
- */
-object Decoupled {
+object DecoupledIO {
+ /** Adds a ready-valid handshaking protocol to any interface.
+ * The standard used is that the consumer uses the flipped interface.
+ */
def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
-}
-/** An I/O bundle for enqueuing data with valid/ready handshaking
- * Initialization must be handled, if necessary, by the parent circuit
- */
-class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
-{
- /** push dat onto the output bits of this interface to let the consumer know it has happened.
- * @param dat the values to assign to bits.
- * @return dat.
- */
- def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
+ implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
+ def firing: Bool = target.ready && target.valid
+
+ /** push dat onto the output bits of this interface to let the consumer know it has happened.
+ * @param dat the values to assign to bits.
+ * @return dat.
+ */
+ def enq(dat: T): T = {
+ target.valid := Bool(true)
+ target.bits := dat
+ dat
+ }
- /** Initialize this Bundle. Valid is set to false, and all bits are set to zero.
- * NOTE: This method of initialization is still being discussed and could change in the
- * future.
- */
- def init(): Unit = {
- valid := Bool(false)
- for (io <- bits.flatten)
- io := UInt(0)
- }
- override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
-}
+ /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero.
+ */
+ def noenq(): Unit = {
+ target.valid := Bool(false)
+ target.bits := target.bits.fromBits(0.asUInt)
+ }
-/** An I/O bundle for dequeuing data with valid/ready handshaking.
- * Initialization must be handled, if necessary, by the parent circuit
- */
-class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
-{
- /** Assert ready on this port and return the associated data bits.
- * This is typically used when valid has been asserted by the producer side.
- * @param b ignored
- * @return the data for this device,
- */
- def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+ /** Assert ready on this port and return the associated data bits.
+ * This is typically used when valid has been asserted by the producer side.
+ * @param b ignored
+ * @return the data for this device,
+ */
+ def deq(): T = {
+ target.ready := Bool(true)
+ target.bits
+ }
- /** Initialize this Bundle.
- * NOTE: This method of initialization is still being discussed and could change in the
- * future.
- */
- def init(): Unit = {
- ready := Bool(false)
+ /** Indicate no dequeue occurs. Ready is set to false
+ */
+ def nodeq(): Unit = {
+ target.ready := Bool(false)
+ }
}
- override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+// override def cloneType: this.type = {
+// DeqIO(gen).asInstanceOf[this.type]
+// }
}
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
-class DecoupledIOC[+T <: Data](gen: T) extends Bundle
-{
- val ready = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val bits = gen.cloneType.asOutput
+object EnqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+}
+object DeqIO {
+ def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
}
/** An I/O Bundle for Queues
@@ -83,11 +76,11 @@ class DecoupledIOC[+T <: Data](gen: T) extends Bundle
class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
{
/** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
- val enq = Decoupled(gen.cloneType).flip()
+ val enq = EnqIO(gen)
/** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
- val deq = Decoupled(gen.cloneType)
+ val deq = DeqIO(gen)
/** The current amount of data in the queue */
- val count = UInt(OUTPUT, log2Up(entries + 1))
+ val count = Output(UInt.width(log2Up(entries + 1)))
}
/** A hardware module implementing a Queue
@@ -110,8 +103,8 @@ class Queue[T <: Data](gen: T, val entries: Int,
extends Module(override_reset=override_reset) {
def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
this(gen, entries, pipe, flow, Some(_reset))
-
- val io = new QueueIO(gen, entries)
+
+ val io = IO(new QueueIO(gen, entries))
val ram = Mem(entries, gen)
val enq_ptr = Counter(entries)
@@ -121,8 +114,8 @@ extends Module(override_reset=override_reset) {
val ptr_match = enq_ptr.value === deq_ptr.value
val empty = ptr_match && !maybe_full
val full = ptr_match && maybe_full
- val do_enq = Wire(init=io.enq.fire())
- val do_deq = Wire(init=io.deq.fire())
+ val do_enq = Wire(init=io.enq.firing)
+ val do_deq = Wire(init=io.deq.firing)
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
@@ -158,9 +151,9 @@ extends Module(override_reset=override_reset) {
} else {
io.count := Mux(ptr_match,
Mux(maybe_full,
- UInt(entries), UInt(0)),
+ UInt.Lit(entries), UInt.Lit(0)),
Mux(deq_ptr.value > enq_ptr.value,
- UInt(entries) + ptr_diff, ptr_diff))
+ UInt.Lit(entries) + ptr_diff, ptr_diff))
}
}
@@ -169,14 +162,14 @@ extends Module(override_reset=override_reset) {
from the inputs.
Example usage:
- {{{ val q = Queue(Decoupled(UInt()), 16)
+ {{{ val q = Queue(DecoupledIO(UInt()), 16)
q.io.enq <> producer.io.out
consumer.io.in <> q.io.deq }}}
*/
object Queue
{
def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = {
- val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
+ val q = Module(new Queue(enq.bits.chiselCloneType, entries, pipe))
q.io.enq.valid := enq.valid // not using <> so that override is allowed
q.io.enq.bits := enq.bits
enq.ready := q.io.enq.ready
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 4d816a19..3a9089c5 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
import chisel3._
object ImplicitConversions {
- implicit def intToUInt(x: Int): UInt = UInt(x)
+ implicit def intToUInt(x: Int): UInt = UInt.Lit(x)
implicit def booleanToBool(x: Boolean): Bool = Bool(x)
}
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index abede61e..49661115 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -31,7 +31,7 @@ object OHToUInt {
* @example {{{ data_out := PriorityEncoder(data_in) }}}
*/
object PriorityEncoder {
- def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+ def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt.Lit(_)))
def apply(in: Bits): UInt = apply(in.toBools)
}
@@ -41,9 +41,9 @@ object UIntToOH
{
def apply(in: UInt, width: Int = -1): UInt =
if (width == -1) {
- UInt(1) << in
+ UInt.Lit(1) << in
} else {
- (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+ (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0)
}
}
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 81de4754..f77a9667 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -26,12 +26,12 @@ object RegEnable
{
def apply[T <: Data](updateData: T, enable: Bool): T = {
val r = Reg(updateData)
- when (enable) { r := updateData }
+ when (enable) { r := updateData.chiselCloneType }
r
}
def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
val r = RegInit(resetData)
- when (enable) { r := updateData }
+ when (enable) { r := updateData.chiselCloneType }
r
}
}
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 78187ff6..743038f3 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -7,20 +7,18 @@ package chisel3.util
import chisel3._
-/** An I/O Bundle containing data and a signal determining if it is valid */
-class ValidIO[+T <: Data](gen2: T) extends Bundle
+/** An Bundle containing data and a signal determining if it is valid */
+class Valid[+T <: Data](gen: T) extends Bundle
{
- val valid = Bool(OUTPUT)
- val bits = gen2.cloneType.asOutput
+ val valid = Output(Bool())
+ val bits = Output(gen.chiselCloneType)
def fire(dummy: Int = 0): Bool = valid
- override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type]
+ override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
}
-/** Adds a valid protocol to any interface. The standard used is
- that the consumer uses the flipped interface.
-*/
+/** Adds a valid protocol to any interface */
object Valid {
- def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen)
+ def apply[T <: Data](gen: T): Valid[T] = new Valid(gen)
}
/** A hardware module that delays data coming down the pipeline
@@ -34,7 +32,7 @@ object Valid {
*/
object Pipe
{
- def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
+ def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
if (latency == 0) {
val out = Wire(Valid(enqBits))
out.valid <> enqValid
@@ -46,16 +44,16 @@ object Pipe
apply(v, b, latency-1)
}
}
- def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1)
- def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency)
+ def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1)
+ def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency)
}
class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
{
- val io = new Bundle {
- val enq = Valid(gen).flip
- val deq = Valid(gen)
- }
+ val io = IO(new Bundle {
+ val enq = Input(Valid(gen))
+ val deq = Output(Valid(gen))
+ })
io.deq <> Pipe(io.enq, latency)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-08 08:57:26 +0000