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Diffstat (limited to 'src/main/scala/chisel3/verilog.scala')
| -rw-r--r-- | src/main/scala/chisel3/verilog.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala index a91444de..b926a15c 100644 --- a/src/main/scala/chisel3/verilog.scala +++ b/src/main/scala/chisel3/verilog.scala @@ -8,8 +8,7 @@ object getVerilogString { } object emitVerilog { - def apply(gen: => RawModule, args: Array[String] = Array.empty, - annotations: AnnotationSeq = Seq.empty): Unit = { + def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): Unit = { (new ChiselStage).emitVerilog(gen, args, annotations) } } |