diff options
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index ef09c07d..451fd039 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -281,7 +281,7 @@ object Queue entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = { - val q = Module(new Queue(enq.bits.cloneType, entries, pipe, flow)) + val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow)) q.io.enq.valid := enq.valid // not using <> so that override is allowed q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 34c4d6d8..34d22a07 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -8,8 +8,7 @@ object RegEnable { /** Returns a register with the specified next, update enable gate, and no reset initialization. */ def apply[T <: Data](next: T, enable: Bool): T = { - val clonedNext = next.chiselCloneType - val r = Reg(clonedNext) + val r = Reg(chiselTypeOf(next)) when (enable) { r := next } r } |