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Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 0bfe7cb3..000fff97 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -44,7 +44,7 @@ object Pipe out.bits <> enqBits out } else { - val v = Reg(Bool(), next=enqValid, init=false.B) + val v = RegNext(enqValid, false.B) val b = RegEnable(enqBits, enqValid) apply(v, b, latency-1) } |