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Diffstat (limited to 'src/main/scala/chisel3/util/Reg.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 34c4d6d8..34d22a07 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -8,8 +8,7 @@ object RegEnable { /** Returns a register with the specified next, update enable gate, and no reset initialization. */ def apply[T <: Data](next: T, enable: Bool): T = { - val clonedNext = next.chiselCloneType - val r = Reg(clonedNext) + val r = Reg(chiselTypeOf(next)) when (enable) { r := next } r } |