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-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 89ad3115..b90e87ac 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,7 +6,7 @@
package chisel3.util
import chisel3._
-import chisel3.experimental.{DataMirror, Direction}
+import chisel3.experimental.{DataMirror, Direction, requireIsChiselType}
import chisel3.internal.naming._ // can't use chisel3_ version because of compile order
/** An I/O Bundle containing 'valid' and 'ready' signals that handshake
@@ -199,7 +199,7 @@ class Queue[T <: Data](gen: T,
}
val genType = if (compileOptions.declaredTypeMustBeUnbound) {
- experimental.requireIsChiselType(gen)
+ requireIsChiselType(gen)
gen
} else {
if (DataMirror.internal.isSynthesizable(gen)) {