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-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index c809e14b..d478e10e 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -7,13 +7,11 @@ package chisel3.util
import chisel3._
-/** Compute the base-2 integer logarithm of a UInt
- * @example
- * {{{ data_out := Log2(data_in) }}}
- * @note The result is truncated, so e.g. Log2(13.U) = 3
- */
object Log2 {
- /** Compute the Log2 on the least significant n bits of x */
+ /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
+ *
+ * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+ */
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
UInt(0)
@@ -30,6 +28,10 @@ object Log2 {
}
}
+ /** Returns the base-2 integer logarithm of an UInt.
+ *
+ * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+ */
def apply(x: Bits): UInt = apply(x, x.getWidth)
private def divideAndConquerThreshold = 4