diff options
Diffstat (limited to 'src/main/scala/chisel3/testers')
| -rw-r--r-- | src/main/scala/chisel3/testers/TesterDriver.scala | 33 |
1 files changed, 10 insertions, 23 deletions
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index 83f3c796..bcbb9cd3 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -21,8 +21,7 @@ object TesterDriver extends BackendCompilationUtilities { /** For use with modules that should successfully be elaborated by the * frontend, and which can be turned into executables with assertions. */ def execute(t: () => BasicTester, - additionalVResources: Seq[String] = Seq(), - runFirrtlasProcess: Boolean = false): Boolean = { + additionalVResources: Seq[String] = Seq()): Boolean = { // Invoke the chisel compiler to get the circuit's IR val circuit = Driver.elaborate(finishWrapper(t)) @@ -46,28 +45,16 @@ object TesterDriver extends BackendCompilationUtilities { out }) - if(runFirrtlasProcess) { - // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& - cppToExe(target, path)).! == 0) { - executeExpectingSuccess(target, path) - } else { - false - } + // Compile firrtl + if (!compileFirrtlToVerilog(target, path)) { + return false } - else { - // Compile firrtl - if (!compileFirrtlToVerilog(target, path)) { - return false - } - // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if ((verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& - cppToExe(target, path)).! == 0) { - executeExpectingSuccess(target, path) - } else { - false - } + // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe + if ((verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& + cppToExe(target, path)).! == 0) { + executeExpectingSuccess(target, path) + } else { + false } } /** |
