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-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index ac4bf8e7..68513423 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -110,7 +110,7 @@ private class Emitter(circuit: Circuit) {
*/
private def moduleDecl(m: Component): String = m.id match {
case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : "
- case _: chisel3.core.UserModule => newline + s"module ${m.name} : "
+ case _: chisel3.core.RawModule => newline + s"module ${m.name} : "
}
/** Generates the FIRRTL module definition.