diff options
Diffstat (limited to 'src/main/scala/chisel3/compatibility.scala')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index c0e933e0..b7020b5e 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -5,11 +5,13 @@ package object Chisel { type Direction = chisel3.core.Direction - val INPUT = chisel3.core.INPUT - val OUTPUT = chisel3.core.OUTPUT - val NO_DIR = chisel3.core.NO_DIR + val INPUT = chisel3.core.Direction.Input + val OUTPUT = chisel3.core.Direction.Output + object Flipped { + def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) + } + type ChiselException = chisel3.internal.ChiselException - type Flipped = chisel3.core.Flipped type Data = chisel3.core.Data val Wire = chisel3.core.Wire val Clock = chisel3.core.Clock @@ -103,10 +105,13 @@ package object Chisel { val Counter = chisel3.util.Counter type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] - val Decoupled = chisel3.util.Decoupled - type EnqIO[T <: Data] = chisel3.util.EnqIO[T] - type DeqIO[T <: Data] = chisel3.util.DeqIO[T] - type DecoupledIOC[+T <: Data] = chisel3.util.DecoupledIOC[T] + val DecoupledIO = chisel3.util.DecoupledIO + object EnqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen)) + } + object DeqIO { + def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) + } type QueueIO[T <: Data] = chisel3.util.QueueIO[T] type Queue[T <: Data] = chisel3.util.Queue[T] val Queue = chisel3.util.Queue @@ -133,7 +138,7 @@ package object Chisel { val RegEnable = chisel3.util.RegEnable val ShiftRegister = chisel3.util.ShiftRegister - type ValidIO[+T <: Data] = chisel3.util.ValidIO[T] + type ValidIO[+T <: Data] = chisel3.util.Valid[T] val Valid = chisel3.util.Valid val Pipe = chisel3.util.Pipe type Pipe[T <: Data] = chisel3.util.Pipe[T] |