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-rw-r--r--src/main/scala/chisel3/Driver.scala19
1 files changed, 16 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f4a7d0e5..f9f6dabe 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -113,10 +113,23 @@ trait BackendCompilationUtilities {
vSources: Seq[File],
cppHarness: File
): ProcessBuilder = {
- val command = Seq("verilator",
- "--cc", s"$dutFile.v") ++
+ val blackBoxVerilogList = {
+ val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.FileListName)
+ if(list_file.exists()) {
+ Seq("-f", list_file.getAbsolutePath)
+ }
+ else {
+ Seq.empty[String]
+ }
+ }
+ val command = Seq(
+ "verilator",
+ "--cc", s"$dutFile.v"
+ ) ++
+ blackBoxVerilogList ++
vSources.map(file => Seq("-v", file.toString)).flatten ++
- Seq("--assert",
+ Seq(
+ "--assert",
"-Wno-fatal",
"-Wno-WIDTH",
"-Wno-STMTDLY",