1 files changed, 7 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 5aeeef99..190b36bf 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -47,7 +47,7 @@ trait BackendCompilationUtilities {
     * C++ sources and headers as well as a makefile to compile them.
     *
     * @param dutFile name of the DUT .v without the .v extension
-    * @param name of the top-level module in the design
+    * @param topModule of the top-level module in the design
     * @param dir output directory
     * @param vSources list of additional Verilog sources to compile
     * @param cppHarness C++ testharness to compile/link against
@@ -86,14 +86,17 @@ trait BackendCompilationUtilities {
   def executeExpectingFailure(
       prefix: String,
       dir: File,
-      assertionMsg: String = "Assertion failed"): Boolean = {
+      assertionMsg: String = ""): Boolean = {
     var triggered = false
+    val assertionMessageSupplied = assertionMsg != ""
     val e = Process(s"./V${prefix}", dir) !
       ProcessLogger(line => {
-        triggered = triggered || line.contains(assertionMsg)
+        triggered = triggered || (assertionMessageSupplied && line.contains(assertionMsg))
         System.out.println(line) // scalastyle:ignore regex
       })
-    triggered
+    // Fail if a line contained an assertion or if we get a non-zero exit code
+    //  or, we get a SIGABRT (assertion failure) and we didn't provide a specific assertion message
+    triggered || (e != 0 && (e != 134 || !assertionMessageSupplied))
   }
 
   def executeExpectingSuccess(prefix: String, dir: File): Boolean = {