3 files changed, 39 insertions, 12 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index b800644d..8f2e1b09 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -280,7 +280,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
     extends Bits(dir, width, lit) with Num[UInt] {
   private[Chisel] override def cloneTypeWidth(w: Width): this.type =
     new UInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"UInt<$width>"
+  private[Chisel] def toType = s"UInt$width"
 
   override private[Chisel] def fromInt(value: BigInt): this.type = UInt(value).asInstanceOf[this.type]
 
@@ -412,7 +412,7 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
     extends Bits(dir, width, lit) with Num[SInt] {
   private[Chisel] override def cloneTypeWidth(w: Width): this.type =
     new SInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"SInt<$width>"
+  private[Chisel] def toType = s"SInt$width"
 
   override def := (that: Data): Unit = that match {
     case _: SInt => this connect that
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 6946652f..60a38a08 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -66,7 +66,7 @@ case class ILit(n: BigInt) extends Arg {
 }
 
 case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name: String = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
+  def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
   def minWidth: Int = 1 max n.bitLength
 
   require(n >= 0, s"UInt literal ${n} is negative")
@@ -117,7 +117,7 @@ sealed case class UnknownWidth() extends Width {
   def known: Boolean = false
   def get: Int = None.get
   def op(that: Width, f: (W, W) => W): Width = this
-  override def toString: String = "?"
+  override def toString: String = ""
 }
 
 sealed case class KnownWidth(value: Int) extends Width {
@@ -128,7 +128,7 @@ sealed case class KnownWidth(value: Int) extends Width {
     case KnownWidth(x) => KnownWidth(f(value, x))
     case _ => that
   }
-  override def toString: String = value.toString
+  override def toString: String = s"<${value.toString}>"
 }
 
 sealed abstract class MemPortDirection(name: String) {
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
index 23a08d52..ba33e6c7 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/Chisel/util/Decoupled.scala
@@ -22,21 +22,48 @@ object Decoupled {
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 }
 
-/** An I/O bundle for enqueuing data with valid/ready handshaking */
+/** An I/O bundle for enqueuing data with valid/ready handshaking
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
 class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
 {
+  /** push dat onto the output bits of this interface to let the consumer know it has happened.
+    * @param dat the values to assign to bits.
+    * @return    dat.
+    */
   def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
-  valid := Bool(false)
-  for (io <- bits.flatten)
-    io := UInt(0)
+
+  /** Initialize this Bundle.  Valid is set to false, and all bits are set to zero.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    valid := Bool(false)
+    for (io <- bits.flatten)
+      io := UInt(0)
+  }
   override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
 }
 
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
+/** An I/O bundle for dequeuing data with valid/ready handshaking.
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
 class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
 {
-  ready := Bool(false)
+  /** Assert ready on this port and return the associated data bits.
+    * This is typically used when valid has been asserted by the producer side.
+    * @param b ignored
+    * @return the data for this device,
+    */
   def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+
+  /** Initialize this Bundle.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    ready := Bool(false)
+  }
   override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
 }
 
@@ -54,7 +81,7 @@ class DecoupledIOC[+T <: Data](gen: T) extends Bundle
 class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
 {
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
-  val enq   = Decoupled(gen.cloneType).flip
+  val enq   = Decoupled(gen.cloneType).flip()
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq   = Decoupled(gen.cloneType)
   /** The current amount of data in the queue */