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-rw-r--r--src/main/scala/Chisel/Tester.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Tester.scala b/src/main/scala/Chisel/Tester.scala
index cf7c7b1c..37923a5f 100644
--- a/src/main/scala/Chisel/Tester.scala
+++ b/src/main/scala/Chisel/Tester.scala
@@ -178,7 +178,7 @@ class ManualTester[+T <: Module]
cmd = "wire_peek " + name;
}
val s = emulatorCmd(cmd)
- val rv = toLitVal(s)
+ val rv = BigInt(s.substring(2), 16)
if (isTrace) println(" PEEK " + name + " " + (if (off >= 0) (off + " ") else "") + "-> " + s)
rv
}