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Diffstat (limited to 'src/main/scala/Chisel/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/IR.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 209e9f64..35211184 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -145,6 +145,7 @@ case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definiti case class DefSeqMemory(id: Data, size: Int) extends Definition case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition +case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command case class WhenElse() extends Command case class WhenEnd() extends Command |