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Diffstat (limited to 'src/main/scala/Chisel/Emitter.scala')
| -rw-r--r-- | src/main/scala/Chisel/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala index 80c6adf0..643135b1 100644 --- a/src/main/scala/Chisel/Emitter.scala +++ b/src/main/scala/Chisel/Emitter.scala @@ -8,6 +8,7 @@ private class Emitter(circuit: Circuit) { private def emit(e: Command, ctx: Component): String = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_+", "+_)})" case e: DefWire => s"wire ${e.name} : ${e.id.toType}" + case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}" case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}" case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}" case e: DefSeqMemory => s"smem ${e.name} : ${e.id.toType}[${e.size}]"; |