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Diffstat (limited to 'src/main/scala/Chisel/Emitter.scala')
| -rw-r--r-- | src/main/scala/Chisel/Emitter.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala index a803c249..c053259d 100644 --- a/src/main/scala/Chisel/Emitter.scala +++ b/src/main/scala/Chisel/Emitter.scala @@ -19,8 +19,6 @@ private class Emitter(circuit: Circuit) { case e: ClockType => s"Clock" } private def emit(e: Command, ctx: Component): String = e match { - case e: DefFlo => s"node ${e.name} = Flo(${e.value})" - case e: DefDbl => s"node ${e.name} = Dbl(${e.value})" case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${join(e.args.map(x => x.fullName(ctx)), ", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.kind)}" case e: DefRegister => s"reg ${e.name} : ${emitType(e.kind)}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}" |