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Diffstat (limited to 'src/main/scala/Chisel/Bits.scala')
| -rw-r--r-- | src/main/scala/Chisel/Bits.scala | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala index 7505c102..57d88244 100644 --- a/src/main/scala/Chisel/Bits.scala +++ b/src/main/scala/Chisel/Bits.scala @@ -321,6 +321,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi def === (that: BitPat): Bool = that === this def != (that: BitPat): Bool = that != this + def =/= (that: BitPat): Bool = that =/= this /** Returns this UInt as a [[SInt]] with an additional zero in the MSB. */ @@ -538,6 +539,9 @@ object Mux { // This returns an lvalue, which it most definitely should not private def doWhen[T <: Data](cond: Bool, con: T, alt: T): T = { require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}") + for ((c, a) <- con.flatten zip alt.flatten) + require(c.width == a.width, "can't Mux between aggregates of different width") + val res = Wire(t = alt.cloneTypeWidth(con.width max alt.width), init = alt) when (cond) { res := con } res |