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Diffstat (limited to 'docs')
| -rw-r--r-- | docs/src/cookbooks/cookbook.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index d4cf3030..ec7e9ed2 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -440,7 +440,7 @@ chisel3.stage.ChiselStage.emitVerilog(new CountBits(4)) ### How do I get Chisel to name signals properly in blocks like when/withClockAndReset? -Use the compiler plugin, and check out the [Naming Cookbook](#naming) if that still does not do what you want. +Use the compiler plugin, and check out the [Naming Cookbook](naming) if that still does not do what you want. ### How do I get Chisel to name the results of vector reads properly? Currently, name information is lost when using dynamic indexing. For example: |