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-rw-r--r--docs/src/explanations/bundles-and-vecs.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/src/explanations/bundles-and-vecs.md b/docs/src/explanations/bundles-and-vecs.md
index 0c8a77b3..dcac31cd 100644
--- a/docs/src/explanations/bundles-and-vecs.md
+++ b/docs/src/explanations/bundles-and-vecs.md
@@ -103,10 +103,10 @@ class MyFlippedModule extends RawModule {
This generates the following Verilog:
-```scala mdoc
+```scala mdoc:verilog
import chisel3.stage.ChiselStage
-println(ChiselStage.emitVerilog(new MyFlippedModule()))
+ChiselStage.emitVerilog(new MyFlippedModule())
```
### MixedVec