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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala2
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala5
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala2
3 files changed, 5 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 9d8a9061..5e88560c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -19,6 +19,8 @@ sealed abstract class Aggregate extends Data {
private[core] def width: Width = flatten.map(_.width).reduce(_ + _)
private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
+
+ override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten)
}
object Vec {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 741f6aee..a5d954b6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -282,9 +282,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref))
}
- @deprecated("Use asUInt, which does the same thing but makes the reinterpret cast more explicit", "chisel3")
- override def toBits: UInt = do_asUInt(DeprecatedSourceInfo)
-
override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
val res = Wire(this, null).asInstanceOf[this.type]
res := that
@@ -463,6 +460,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
override def do_<= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessEqOp, that)
override def do_>= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, GreaterEqOp, that)
+ @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
final def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
final def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
final def === (that: UInt): Bool = macro SourceInfoTransform.thatArg
@@ -658,6 +656,7 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
override def do_<= (that: SInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessEqOp, that)
override def do_>= (that: SInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, GreaterEqOp, that)
+ @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
final def != (that: SInt): Bool = macro SourceInfoTransform.thatArg
final def =/= (that: SInt): Bool = macro SourceInfoTransform.thatArg
final def === (that: SInt): Bool = macro SourceInfoTransform.thatArg
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index bd2e9065..86858e5d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -254,7 +254,7 @@ abstract class Data extends HasId {
*
* This performs the inverse operation of fromBits(Bits).
*/
- @deprecated("Use asUInt, which does the same thing but makes the reinterpret cast more explicit", "chisel3")
+ @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
/** Reinterpret cast to UInt.