diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 70e9938b..64d7d5fd 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -1,11 +1,11 @@ // See LICENSE for license details. -package chisel.internal.firrtl +package chisel3.internal.firrtl -import chisel._ +import chisel3._ import core._ -import chisel.internal._ -import chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo} +import chisel3.internal._ +import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo} case class PrimOp(val name: String) { override def toString: String = name @@ -55,8 +55,8 @@ case class Node(id: HasId) extends Arg { } abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { - private[chisel] def forcedWidth = widthArg.known - private[chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth) + private[chisel3] def forcedWidth = widthArg.known + private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) protected def minWidth: Int if (forcedWidth) { |