1 files changed, 20 insertions, 3 deletions
diff --git a/AbstractModule.scala b/AbstractModule.scala
index 2c2574ad..10aca713 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -2,15 +2,32 @@ package chiselTests
 
 import chisel3._
 import chisel3.stage.ChiselStage
+import chisel3.MetaConnect._
+
+
+object TypeArithmetic {
+  implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
+  implicit val f2: SomeTypeContainer => Unit => SomeTypeContainer = (a: SomeTypeContainer) => (b: Unit) => a
+}
+
+case class SomeTypeContainer(w: Int) extends UInt(w.W)
 
 class AbstractModule[T <: Data](params: T) extends Module[T] {
   val node = IO(params)
 }
 
 class AbstractModuleContainer extends Module {
-  val mod1 = Module(new AbstractModule[UInt](Input(UInt(0.W))))
-  val mod2 = Module(new AbstractModule[UInt](Output(UInt(0.W))))
-  mod2.node := mod1.node
+  val mod1 = Module(new AbstractModule[UInt](Input(UInt(4.W))))
+  val mod2 = Module(new AbstractModule[UInt](Output(UInt(8.W))))
+
+  val tc = SomeTypeContainer(16)
+  val mod3 = Module(new AbstractModule[tc.type](Output(tc)))
+
+  import TypeArithmetic._
+  mod3.node.makeConnection(mod1.node.makeConnection(mod2.node))
+
+  // goal is to get this to work:
+  // mod1.node := mod2.node := mod3.node
 }
 
 object main {