diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Data.scala | 9 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/RecordSpec.scala | 20 |
2 files changed, 27 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 50093333..dddc0d5d 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -256,8 +256,13 @@ package experimental { def fullModulePorts(target: BaseModule): Seq[(String, Data)] = { def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match { case _: Element => Seq() - case r: Record => r.elements.toSeq.flatMap { case (eltName, elt) => getPortNames(s"${name}_${eltName}", elt) } - case v: Vec[_] => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) } + case r: Record => + r.elements.toSeq.flatMap { + case (eltName, elt) => + if (r._isOpaqueType) { getPortNames(s"${name}", elt) } + else { getPortNames(s"${name}_${eltName}", elt) } + } + case v: Vec[_] => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) } }) modulePorts(target).flatMap { case (name, data) => diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 3414ec8a..5a5bcf67 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -284,6 +284,26 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils { testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo")) } + they should "work correctly with DataMirror in nested OpaqueType Records" in { + var mod: NestedRecordModule = null + ChiselStage.elaborate { mod = new NestedRecordModule; mod } + val ports = chisel3.experimental.DataMirror.fullModulePorts(mod.inst) + val expectedPorts = Seq( + ("clock", mod.inst.clock), + ("reset", mod.inst.reset), + ("io", mod.inst.io), + ("io_bar", mod.inst.io.bar), + ("io_bar", mod.inst.io.bar.k), + ("io_bar", mod.inst.io.bar.k.k), + ("io_bar", mod.inst.io.bar.k.k.elements.head._2), + ("io_foo", mod.inst.io.foo), + ("io_foo", mod.inst.io.foo.k), + ("io_foo", mod.inst.io.foo.k.k), + ("io_foo", mod.inst.io.foo.k.k.elements.head._2) + ) + ports shouldBe expectedPorts + } + they should "work correctly when connecting nested OpaqueType elements" in { val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule } nestedRecordChirrtl should include("input in : UInt<8>") |