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-rw-r--r--src/test/scala/chiselTests/experimental/FlatIOSpec.scala8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
index ebb7cbdb..fb3f64c7 100644
--- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
+++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -55,9 +55,11 @@ class FlatIOSpec extends ChiselFlatSpec {
val bar = Analog(8.W)
}
class MyModule extends RawModule {
- val in = IO(Flipped(new MyBundle))
- val out = IO(new MyBundle)
- out <> in
+ val io = FlatIO(new Bundle {
+ val in = Flipped(new MyBundle)
+ val out = new MyBundle
+ })
+ io.out <> io.in
}
val chirrtl = emitChirrtl(new MyModule)
chirrtl should include("out.foo <= in.foo")