diff options
18 files changed, 95 insertions, 376 deletions
@@ -4,164 +4,22 @@ import com.typesafe.tools.mima.core._ Compile / compile / logLevel := Level.Error -// enablePlugins(SiteScaladocPlugin) - val scala3Version = "3.4.1" lazy val commonSettings = Seq ( - resolvers ++= Seq( - Resolver.sonatypeRepo("snapshots"), - Resolver.sonatypeRepo("releases") - ), organization := "edu.berkeley.cs", version := "3.5.6", autoAPIMappings := true, scalaVersion := scala3Version, crossScalaVersions := Seq("2.13.10", "2.12.17", scala3Version), - scalacOptions := Seq("-rewrite", "-source:3.4-migration"), - // libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - // Macros paradise is integrated into 2.13 but requires a scalacOption - scalacOptions ++= { - CrossVersion.partialVersion(scalaVersion.value) match { - case Some((2, n)) if n >= 13 => "-Ymacro-annotations" :: Nil - case _ => Nil - } - }, - // libraryDependencies ++= { - // CrossVersion.partialVersion(scalaVersion.value) match { - // case Some((2, n)) if n >= 13 => Nil - // case _ => compilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) :: Nil - // } - // } -) - -lazy val publishSettings = Seq ( - versionScheme := Some("pvp"), - publishMavenStyle := true, - publishArtifact in Test := false, - pomIncludeRepository := { x => false }, - pomExtra := <url>http://chisel.eecs.berkeley.edu/</url> - <licenses> - <license> - <name>apache-v2</name> - <url>https://opensource.org/licenses/Apache-2.0</url> - <distribution>repo</distribution> - </license> - </licenses> - <developers> - <developer> - <id>jackbackrack</id> - <name>Jonathan Bachrach</name> - <url>http://www.eecs.berkeley.edu/~jrb/</url> - </developer> - </developers>, - - publishTo := { - val v = version.value - val nexus = "https://oss.sonatype.org/" - if (v.trim.endsWith("SNAPSHOT")) { - Some("snapshots" at nexus + "content/repositories/snapshots") - } - else { - Some("releases" at nexus + "service/local/staging/deploy/maven2") - } - } + scalacOptions := Seq("-rewrite", "-source:3.4-migration") ) lazy val chiselSettings = Seq ( name := "chisel3", ) -// autoCompilerPlugins := true - -// Plugin must be fully cross-versioned (published for Scala minor version) -// The plugin only works in Scala 2.12+ -// lazy val pluginScalaVersions = Seq( -// // scalamacros paradise version used is not published for 2.12.0 and 2.12.1 -// "2.12.2", -// "2.12.3", -// "2.12.4", -// "2.12.5", -// "2.12.6", -// "2.12.7", -// "2.12.8", -// "2.12.9", -// "2.12.10", -// "2.12.11", -// "2.12.12", -// "2.12.13", -// "2.12.14", -// "2.12.15", -// "2.12.16", -// "2.12.17", -// "2.13.0", -// "2.13.1", -// "2.13.2", -// "2.13.3", -// "2.13.4", -// "2.13.5", -// "2.13.6", -// "2.13.7", -// "2.13.8", -// "2.13.9", -// "2.13.10", -// ) - -// lazy val plugin = (project in file("plugin")). -// settings(name := "chisel3-plugin"). -// settings(commonSettings: _*). -// settings(publishSettings: _*). -// settings( -// // libraryDependencies += "org.scala-lang" % "scala-compiler" % scalaVersion.value, -// scalacOptions += "-Xfatal-warnings", -// crossScalaVersions := pluginScalaVersions, -// // Must be published for Scala minor version -// crossVersion := CrossVersion.full, -// crossTarget := { -// // workaround for https://github.com/sbt/sbt/issues/5097 -// target.value / s"scala-${scalaVersion.value}" -// } -// ). -// settings( -// // Given that the plugin is 1) a compile-time only dependency and 2) package chisel3.internal, -// // I'm not really sure why we both checking binary compatbility -// mimaBinaryIssueFilters ++= Seq( -// // MyTypingTransformer is private (https://github.com/lightbend/mima/issues/53) -// ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.internal.plugin.BundleComponent#MyTypingTransformer.isBundle"), -// ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.internal.plugin.BundleComponent#MyTypingTransformer.getConstructorAndParams") -// ), -// mimaPreviousArtifacts := { -// // There are not yet artifacts for 2.12.17, 2.13.9, nor 2.13.10; suppress until 3.5.5 is released -// val skipVersions = Seq("2.12.17", "2.13.9", "2.13.10") -// if (skipVersions.contains(scalaVersion.value)) { -// Set() -// } else { -// Set("edu.berkeley.cs" % "chisel3-plugin" % "3.5.4" cross CrossVersion.full) -// } -// } -// ) - -// lazy val usePluginSettings = Seq( -// scalacOptions in Compile ++= { -// val jar = (plugin / Compile / Keys.`package`).value -// val addPlugin = "-Xplugin:" + jar.getAbsolutePath -// // add plugin timestamp to compiler options to trigger recompile of -// // main after editing the plugin. (Otherwise a 'clean' is needed.) -// val dummy = "-Jdummy=" + jar.lastModified -// Seq(addPlugin, dummy) -// } -// ) - -// lazy val macros = (project in file("macros")). -// settings(name := "chisel3-macros"). -// settings(commonSettings: _*). -// settings(publishSettings: _*). -// settings(mimaPreviousArtifacts := Set("edu.berkeley.cs" %% "chisel3-macros" % "3.5.4")) - -// lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") - lazy val core = (project in file("core")). - // sourceDependency(firrtlRef, defaultVersions("firrtl")). settings(commonSettings: _*). enablePlugins(BuildInfoPlugin). settings( @@ -169,133 +27,31 @@ lazy val core = (project in file("core")). buildInfoUsePackageAsPath := true, buildInfoKeys := Seq[BuildInfoKey](buildInfoPackage, version, scalaVersion, sbtVersion) ). - settings(publishSettings: _*). settings( libraryDependencies += "edu.berkeley.cs" % "firrtl_3" % "1.6-SNAPSHOT", - mimaPreviousArtifacts := Set("edu.berkeley.cs" %% "chisel3-core" % "3.5.4"), - mimaBinaryIssueFilters ++= Seq( - // This is not a problem because the relevant method is implemented (and final) in Vec and Record - ProblemFilters.exclude[ReversedMissingMethodProblem]("chisel3.Aggregate.elementsIterator"), - // Modified package private methods (https://github.com/lightbend/mima/issues/53) - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.Data._computeName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.Data.forceName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.MemBase._computeName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.MemBase.forceName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.VerificationStatement._computeName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.VerificationStatement.forceName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.experimental.BaseModule._computeName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.experimental.BaseModule.forceName"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.VerificationStatement.failureMessage"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.Data.setRef"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.MemBase.setRef"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.VerificationStatement.setRef"), - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.experimental.BaseModule.setRef"), - // Methods in inner class defined within package private object - ProblemFilters.exclude[IncompatibleResultTypeProblem]("chisel3.internal.firrtl.Converter#WhenFrame.outer"), - ProblemFilters.exclude[IncompatibleMethTypeProblem]("chisel3.internal.firrtl.Converter#WhenFrame.copy"), - ProblemFilters.exclude[IncompatibleResultTypeProblem]("chisel3.internal.firrtl.Converter#WhenFrame.copy$default$2"), - ProblemFilters.exclude[IncompatibleMethTypeProblem]("chisel3.internal.firrtl.Converter#WhenFrame.this"), - ProblemFilters.exclude[IncompatibleMethTypeProblem]("chisel3.internal.firrtl.Converter#WhenFrame.apply"), - ) ). settings( name := "chisel3-core", scalacOptions := scalacOptions.value ++ Seq( - "-deprecation", "-explaintypes", "-feature", "-language:reflectiveCalls", "-unchecked", - "-Xcheckinit", - "-Xlint:infer-any" -// , "-Xlint:missing-interpolator" ) ) - // dependsOn(macros) // This will always be the root project, even if we are a sub-project. lazy val root = RootProject(file(".")) lazy val chisel = (project in file(".")). - // enablePlugins(ScalaUnidocPlugin). settings(commonSettings: _*). settings(chiselSettings: _*). - settings(publishSettings: _*). - // settings(usePluginSettings: _*). - // dependsOn(macros). dependsOn(core). aggregate(core). settings( - mimaPreviousArtifacts := Set("edu.berkeley.cs" %% "chisel3" % "3.5.4"), - mimaBinaryIssueFilters ++= Seq( - // Modified package private methods (https://github.com/lightbend/mima/issues/53) - ProblemFilters.exclude[DirectMissingMethodProblem]("chisel3.stage.ChiselOptions.this"), - ), - // libraryDependencies += defaultVersions("treadle") % "test", - // Test / scalacOptions += "-P:chiselplugin:genBundleElements", - // Forward doc command to unidoc - // Compile / doc := (ScalaUnidoc / doc).value, - // Include unidoc as the ScalaDoc for publishing - // Compile / packageDoc / mappings := (ScalaUnidoc / packageDoc / mappings).value, scalacOptions in Test ++= Seq("-language:reflectiveCalls"), - scalacOptions in Compile in doc ++= Seq( - "-diagrams", - "-groups", - "-skip-packages", "chisel3.internal", - "-diagrams-max-classes", "25", - "-doc-version", version.value, - "-doc-title", name.value, - "-doc-root-content", baseDirectory.value+"/root-doc.txt", - "-sourcepath", (baseDirectory in ThisBuild).value.toString, - "-doc-source-url", - { - val branch = - if (version.value.endsWith("-SNAPSHOT")) { - "master" - } else { - s"v${version.value}" - } - s"https://github.com/chipsalliance/chisel3/tree/$branch€{FILE_PATH_EXT}#L€{FILE_LINE}" - } - ) - // Suppress compiler plugin for source files in core - // We don't need this in regular compile because we just don't add the chisel3-plugin to core's scalacOptions - // This works around an issue where unidoc uses the exact same arguments for all source files. - // This is probably fundamental to how ScalaDoc works so there may be no solution other than this workaround. - // See https://github.com/sbt/sbt-unidoc/issues/107 - // (core / Compile / sources).value.map("-P:chiselplugin:INTERNALskipFile:" + _) ) -// tests elaborating and executing/formally verifying a Chisel circuit with chiseltest -lazy val integrationTests = (project in file ("integration-tests")). - dependsOn(chisel). - settings(commonSettings: _*). - settings(chiselSettings: _*). - // settings(usePluginSettings: _*). - settings(Seq( - libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5-SNAPSHOT" % "test" - )) - -// lazy val docs = project // new documentation project -// .in(file("docs-target")) // important: it must not be docs/ -// .dependsOn(chisel) -// // .enablePlugins(MdocPlugin) -// // .settings(usePluginSettings: _*) -// .settings(commonSettings) -// .settings( -// scalacOptions ++= Seq( -// "-language:reflectiveCalls", -// "-language:implicitConversions" -// ), -// mdocIn := file("docs/src"), -// mdocOut := file("docs/generated"), -// // None of our links are hygienic because they're primarily used on the website with .html -// mdocExtraArguments := Seq("--cwd", "docs", "--no-link-hygiene"), -// mdocVariables := Map( -// "BUILD_DIR" -> "docs-target" // build dir for mdoc programs to dump temp files -// ) -// ) - addCommandAlias("com", "all compile") addCommandAlias("lint", "; compile:scalafix --check ; test:scalafix --check") addCommandAlias("fix", "all compile:scalafix test:scalafix") diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index 52d96ce6..a3a8470f 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -67,8 +67,8 @@ sealed abstract class Aggregate extends Data { } } - override def asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { - SeqUtils.asUInt(flatten.map(_.asUInt())) + override def asUInt(using sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + SeqUtils.asUInt(flatten.map(_.asUInt)) } private[chisel3] override def connectFromBits( @@ -94,13 +94,13 @@ sealed abstract class Aggregate extends Data { } } -trait VecFactory { +object Vec { /** Creates a new [[Vec]] with `n` entries of the specified data type. * * @note elements are NOT assigned by default and have no value */ - def apply[T <: Data](n: Int, gen: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { + def apply[T <: Data](n: Int, gen: T)(using sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { if (compileOptions.declaredTypeMustBeUnbound) { requireIsChiselType(gen, "vec type") } @@ -146,7 +146,7 @@ trait VecFactory { * - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined) * - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier */ -sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate with VecLike[T] { +sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate { override def toString: String = { topBindingOpt match { diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala index b73eaa8a..ffcd7c95 100644 --- a/core/src/main/scala/chisel3/Bits.scala +++ b/core/src/main/scala/chisel3/Bits.scala @@ -5,13 +5,7 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushOp import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{ - IntLiteralApplyTransform, - SourceInfo, - SourceInfoTransform, - SourceInfoWhiteboxTransform, - UIntTransform -} +import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.firrtl.PrimOp._ import _root_.firrtl.{ir => firrtlir} import _root_.firrtl.{constraint => firrtlconstraint} @@ -106,7 +100,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return the specified bit */ final def apply(x: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - do_extract(x) + extract(x) /** Returns the specified bit on this $coll as a [[Bool]], statically addressed. * @@ -114,7 +108,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return the specified bit */ final def apply(x: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - do_extract(BigInt(x)) + extract(BigInt(x)) /** Returns the specified bit on this wire as a [[Bool]], dynamically addressed. * @@ -132,7 +126,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return the specified bit */ final def apply(x: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = - do_extract(x) + extract(x) /** Returns a subset of bits on this $coll from `hi` to `lo` (inclusive), statically addressed. * @@ -180,7 +174,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi * @return a hardware component contain the requested bits */ final def apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - do_apply(castToInt(x, "High index"), castToInt(y, "Low index")) + apply(castToInt(x, "High index"), castToInt(y, "Low index")) private[chisel3] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = { requireIsHardware(this, "bits operated on") @@ -320,6 +314,20 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi } } +object Bits { + def apply(): UInt = apply(Width()) + + /** Create a UInt port with specified width. */ + def apply(width: Width): UInt = new UInt(width) + + /** Create a UInt literal with specified width. */ + protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { + val lit = ULit(value, width) + val result = new UInt(lit.width) + // Bind result to being an Literal + lit.bindLitArg(result) + } +} /** A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other * integer types. * @@ -569,8 +577,8 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U def rotateLeft(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = width match { case _ if (n == 0) => this case KnownWidth(w) if (w <= 1) => this - case KnownWidth(w) if n >= w => do_rotateLeft(n % w) - case _ if (n < 0) => do_rotateRight(-n) + case KnownWidth(w) if n >= w => rotateLeft(n % w) + case _ if (n < 0) => rotateRight(-n) case _ => tail(n) ## head(n) } @@ -580,9 +588,9 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U * @return UInt of same width rotated right n bits */ def rotateRight(n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = width match { - case _ if (n <= 0) => do_rotateLeft(-n) + case _ if (n <= 0) => rotateLeft(-n) case KnownWidth(w) if (w <= 1) => this - case KnownWidth(w) if n >= w => do_rotateRight(n % w) + case KnownWidth(w) if n >= w => rotateRight(n % w) case _ => this(n - 1, 0) ## (this >> n) } @@ -590,7 +598,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U n: UInt, staticShift: (UInt, Int) => UInt )( - implicit sourceInfo: SourceInfo, + using sourceInfo: SourceInfo, compileOptions: CompileOptions ): UInt = n.asBools().zipWithIndex.foldLeft(this) { @@ -646,6 +654,20 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U binop(sourceInfo, SInt((this.width.max(that.width)) + 1), SubOp, that) } +object UInt { + def apply(): UInt = apply(Width()) + + /** Create a UInt port with specified width. */ + def apply(width: Width): UInt = new UInt(width) + + /** Create a UInt literal with specified width. */ + protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { + val lit = ULit(value, width) + val result = new UInt(lit.width) + // Bind result to being an Literal + lit.bindLitArg(result) + } +} /** A data type for signed integers, represented as a binary bitvector. Defines arithmetic operations between other * integer types. * @@ -662,6 +684,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S } } + private[chisel3] override def typeEquivalent(that: Data): Boolean = this.getClass == that.getClass && this.width == that.width // TODO: should this be true for unspecified widths? @@ -853,6 +876,21 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S } } +object SInt { + /** Create an SInt type with inferred width. */ + def apply(): SInt = apply(Width()) + + /** Create a SInt type or port with fixed width. */ + def apply(width: Width): SInt = new SInt(width) + + /** Create an SInt literal with specified width. */ + protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { + val lit = SLit(value, width) + val result = new SInt(lit.width) + lit.bindLitArg(result) + } +} + sealed trait Reset extends Element with ToBoolable { /** Casts this $coll to an [[AsyncReset]] */ @@ -1050,6 +1088,15 @@ sealed class Bool() extends UInt(1.W) with Reset { pushOp(DefPrim(sourceInfo, AsyncReset(), AsAsyncResetOp, ref)) } +object Bool { + def Lit(x: Boolean): Bool = { + val result = new Bool() + val lit = ULit(if (x) 1 else 0, Width(1)) + lit.bindLitArg(result) + } + def apply(): Bool = new Bool() +} + package experimental { import chisel3.internal.firrtl.BinaryPoint diff --git a/core/src/main/scala/chisel3/BoolFactory.scala b/core/src/main/scala/chisel3/BoolFactory.scala deleted file mode 100644 index 1d96659f..00000000 --- a/core/src/main/scala/chisel3/BoolFactory.scala +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package chisel3 - -import chisel3.internal.firrtl.{ULit, Width} - -trait BoolFactory { - - /** Creates an empty Bool. - */ - def apply(): Bool = new Bool() - - /** Creates Bool literal. - */ - protected[chisel3] def Lit(x: Boolean): Bool = { - val result = new Bool() - val lit = ULit(if (x) 1 else 0, Width(1)) - // Ensure we have something capable of generating a name. - lit.bindLitArg(result) - } -} diff --git a/core/src/main/scala/chisel3/CompileOptions.scala b/core/src/main/scala/chisel3/CompileOptions.scala index f74d8fff..cdc05392 100644 --- a/core/src/main/scala/chisel3/CompileOptions.scala +++ b/core/src/main/scala/chisel3/CompileOptions.scala @@ -63,7 +63,7 @@ object ExplicitCompileOptions { // Collection of "not strict" connection compile options. // These provide compatibility with existing code. - implicit val NotStrict = new CompileOptionsClass( + implicit val NotStrict: CompileOptionsClass = new CompileOptionsClass( connectFieldsMustMatch = false, declaredTypeMustBeUnbound = false, dontTryConnectionsSwapped = false, @@ -97,7 +97,7 @@ object ExplicitCompileOptions { } // Collection of "strict" connection compile options, preferred for new code. - implicit val Strict = new CompileOptionsClass( + implicit val Strict: CompileOptionsClass = new CompileOptionsClass( connectFieldsMustMatch = true, declaredTypeMustBeUnbound = true, dontTryConnectionsSwapped = true, diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index a80392f6..5f9af175 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -6,7 +6,7 @@ import chisel3.experimental.{Analog, BaseModule, DataMirror} import chisel3.internal.Builder.pushCommand import chisel3.internal._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, UnlocatableSourceInfo} +import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo} import scala.collection.immutable.LazyList // Needed for 2.12 alias import scala.reflect.ClassTag diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala index 9180cb63..41ae5879 100644 --- a/core/src/main/scala/chisel3/Mem.scala +++ b/core/src/main/scala/chisel3/Mem.scala @@ -7,7 +7,7 @@ import firrtl.{ir => fir} import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{MemTransform, SourceInfo, SourceInfoTransform, SourceLine, UnlocatableSourceInfo} +import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo} object Mem { @@ -104,7 +104,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) def read(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = apply_impl(idx, clock, MemPortDirection.READ, false) - protected def do_apply_impl( + protected def apply_impl( idx: UInt, clock: Clock, dir: MemPortDirection, @@ -225,7 +225,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) dir: MemPortDirection, clock: Clock )( - implicit compileOptions: CompileOptions + using compileOptions: CompileOptions ): T = { if (Builder.currentModule != _parent) { throwException( @@ -233,7 +233,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) ) } requireIsHardware(idx, "memory port index") - val i = Vec.truncateIndex(idx, length)(sourceInfo, compileOptions) + val i = Vec.truncateIndex(idx, length)(compileOptions) val port = pushCommand( DefMemPort(sourceInfo, t.cloneTypeFull, Node(this), dir, i.ref, clock.ref) @@ -347,7 +347,7 @@ sealed class SyncReadMem[T <: Data] private[chisel3] (t: T, n: BigInt, val readU clock: Clock, warn: Boolean )( - implicit sourceInfo: SourceInfo, + using sourceInfo: SourceInfo, compileOptions: CompileOptions ): T = { val a = Wire(UInt(4.W)) @@ -355,7 +355,7 @@ sealed class SyncReadMem[T <: Data] private[chisel3] (t: T, n: BigInt, val readU var port: Option[T] = None when(enable) { a := addr - port = Some(super.do_apply_impl(a, clock, MemPortDirection.READ, warn)) + port = Some(super.apply(a, clock, MemPortDirection.READ, warn)) } port.get } diff --git a/core/src/main/scala/chisel3/Mux.scala b/core/src/main/scala/chisel3/Mux.scala index 48006bd1..a1f5a86d 100644 --- a/core/src/main/scala/chisel3/Mux.scala +++ b/core/src/main/scala/chisel3/Mux.scala @@ -4,7 +4,7 @@ package chisel3 import chisel3.internal._ import chisel3.internal.Builder.pushOp -import chisel3.internal.sourceinfo.{MuxTransform, SourceInfo} +import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.firrtl._ import chisel3.internal.firrtl.PrimOp._ diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala deleted file mode 100644 index 8cceda13..00000000 --- a/core/src/main/scala/chisel3/SIntFactory.scala +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package chisel3 - -import chisel3.internal.firrtl.{SLit, Width} - -trait SIntFactory { - - /** Create an SInt type with inferred width. */ - def apply(): SInt = apply(Width()) - - /** Create a SInt type or port with fixed width. */ - def apply(width: Width): SInt = new SInt(width) - - /** Create an SInt literal with specified width. */ - protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { - val lit = SLit(value, width) - val result = new SInt(lit.width) - lit.bindLitArg(result) - } -} diff --git a/core/src/main/scala/chisel3/UIntFactory.scala b/core/src/main/scala/chisel3/UIntFactory.scala deleted file mode 100644 index 66c6f9c8..00000000 --- a/core/src/main/scala/chisel3/UIntFactory.scala +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package chisel3 - -import chisel3.internal.firrtl.{KnownWidth, ULit, UnknownWidth, Width} -import firrtl.Utils -import firrtl.constraint.IsKnown -import firrtl.ir.{Closed, IntWidth, Open} - -// This is currently a factory because both Bits and UInt inherit it. -trait UIntFactory { - - /** Create a UInt type with inferred width. */ - def apply(): UInt = apply(Width()) - - /** Create a UInt port with specified width. */ - def apply(width: Width): UInt = new UInt(width) - - /** Create a UInt literal with specified width. */ - protected[chisel3] def Lit(value: BigInt, width: Width): UInt = { - val lit = ULit(value, width) - val result = new UInt(lit.width) - // Bind result to being an Literal - lit.bindLitArg(result) - } -} diff --git a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala index 27b07199..b8317a02 100644 --- a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala +++ b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala @@ -145,7 +145,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating * @param s a [[scala.collection.Seq$ Seq]] of enumeration values to look for * @return a hardware [[Bool]] that indicates if this value matches any of the given values */ - final def isOneOf(s: Seq[EnumType])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { + final def isOneOf(s: Seq[EnumType])(using sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { VecInit(s.map(this === _)).asUInt().orR() } @@ -333,7 +333,7 @@ abstract class EnumFactory { } this.id = id.litValue - do_Value(name) + Value(name) } def apply(): Type = new Type diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala index e803c775..f4575ceb 100644 --- a/core/src/main/scala/chisel3/experimental/package.scala +++ b/core/src/main/scala/chisel3/experimental/package.scala @@ -153,8 +153,8 @@ package object experimental { */ def Lit[T <: Data](elems: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = { require(elems.nonEmpty, s"Lit.Vec(...) must have at least one element") - val indexElements = elems.zipWithIndex.map { case (element, index) => (index, element) } - val widestElement = elems.maxBy(_.getWidth) + val indexElements: Seq[(Int, T)] = elems.zipWithIndex.map { case (element, index) => (index, element) } + val widestElement: T = elems.maxBy(_.getWidth) val vec: Vec[T] = Vec.apply(indexElements.length, chiselTypeOf(widestElement)) vec.Lit(indexElements: _*) } diff --git a/core/src/main/scala/chisel3/internal/Binding.scala b/core/src/main/scala/chisel3/internal/Binding.scala index 63936212..3a12afde 100644 --- a/core/src/main/scala/chisel3/internal/Binding.scala +++ b/core/src/main/scala/chisel3/internal/Binding.scala @@ -13,7 +13,7 @@ import scala.collection.immutable.VectorMap object requireIsHardware { def apply(node: Data, msg: String = ""): Unit = { node._parent match { // Compatibility layer hack - case Some(x: BaseModule) => x._compatAutoWrapPorts + case Some(x: BaseModule) => x._compatAutoWrapPorts() case _ => } if (!node.isSynthesizable) { diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index 57f878aa..0a63bc74 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -791,7 +791,7 @@ object DynamicNamingStack { prefixRef } - def length(): Int = Builder.namingStackOption.get.length + def length(): Int = Builder.namingStackOption.get.length() } /** Casts BigInt to Int, issuing an error when the input isn't representable. */ diff --git a/core/src/main/scala/chisel3/internal/Namer.scala b/core/src/main/scala/chisel3/internal/Namer.scala index 23b5b7ba..45efa052 100644 --- a/core/src/main/scala/chisel3/internal/Namer.scala +++ b/core/src/main/scala/chisel3/internal/Namer.scala @@ -3,7 +3,6 @@ // This file contains part of the implementation of the naming static annotation system. package chisel3.internal.naming -import chisel3.experimental.NoChiselNamePrefix import scala.collection.mutable.Stack import scala.collection.mutable.ListBuffer @@ -97,7 +96,6 @@ class NamingContext extends NamingContextInterface { def name[T](obj: T, name: String): T = { assert(!closed, "Can't name elements after namePrefix called") obj match { - case _: NoChiselNamePrefix => // Don't name things with NoChiselNamePrefix case ref: AnyRef => items += ((ref, name)) case _ => } diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index c9719498..93676fef 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -160,8 +160,6 @@ private[chisel3] object Converter { Some(fir.IsInvalid(convert(info), convert(arg, ctx, info))) case e @ DefInstance(info, id, _) => Some(fir.DefInstance(convert(info), e.name, id.name)) - case e @ Stop(_, info, clock, ret) => - Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name)) case e @ Printf(_, info, clock, pable) => val (fmt, args) = unpack(pable, ctx) Some( diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 8ed5ed07..0e0ebef2 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -332,12 +332,7 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition -// Note this is just deprecated which will cause deprecation warnings, use @nowarn -@deprecated( - "This API should never have been public, for Module port reflection, use DataMirror.modulePorts", - "Chisel 3.5" -) + case class Port(id: Data, dir: SpecifiedDirection) case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition object Formal extends Enumeration { @@ -345,15 +340,7 @@ object Formal extends Enumeration { val Assume = Value("assume") val Cover = Value("cover") } -case class Verification[T <: VerificationStatement]( - id: T, - op: Formal.Value, - sourceInfo: SourceInfo, - clock: Arg, - predicate: Arg, - message: String) - extends Definition -@nowarn("msg=class Port") // delete when Port becomes private + abstract class Component extends Arg { def id: BaseModule def name: String diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala index d30a5c83..f69c6d04 100644 --- a/core/src/main/scala/chisel3/package.scala +++ b/core/src/main/scala/chisel3/package.scala @@ -3,11 +3,12 @@ import chisel3.internal.firrtl.BinaryPoint import java.util.{MissingFormatArgumentException, UnknownFormatConversionException} import scala.collection.mutable +import chisel3.experimental.VecLiterals._ +import chisel3.experimental.BundleLiterals._ /** This package contains the main chisel3 API. */ package object chisel3 { - import internal.chiselRuntimeDeprecated import internal.sourceinfo.DeprecatedSourceInfo import internal.firrtl.{Port, Width} import internal.Builder @@ -158,7 +159,7 @@ package object chisel3 { val WireInit = WireDefault - object Vec extends VecFactory + // object Vec extends VecFactory // Some possible regex replacements for the literal specifier deprecation: // (note: these are not guaranteed to handle all edge cases! check all replacements!) @@ -174,13 +175,13 @@ package object chisel3 { // => $1.U($2.W) // (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) // => $2.as$1 - // (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) + // (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)n // => $2.as$1($3.W) - object Bits extends UIntFactory - object UInt extends UIntFactory - object SInt extends SIntFactory - object Bool extends BoolFactory + // object Bits extends UIntFactory + // object UInt extends UIntFactory + // object SInt extends SIntFactory + // object Bool extends BoolFactory type InstanceId = internal.InstanceId |