summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--docs/src/cookbooks/cookbook.md7
1 files changed, 3 insertions, 4 deletions
diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md
index ce49b668..4b2b088e 100644
--- a/docs/src/cookbooks/cookbook.md
+++ b/docs/src/cookbooks/cookbook.md
@@ -88,13 +88,14 @@ you are tying off, you can use `chiselTypeOf`:
```scala mdoc:silent:reset
import chisel3._
+import chisel3.stage.ChiselStage
class MyBundle extends Bundle {
val foo = UInt(4.W)
val bar = Vec(4, UInt(1.W))
}
-class Foo(typ: Data) extends RawModule {
+class Foo(typ: MyBundle) extends RawModule {
val bundleA = IO(Output(typ))
val bundleB = IO(Output(typ))
@@ -107,9 +108,7 @@ class Foo(typ: Data) extends RawModule {
bundleB := 0.U.asTypeOf(chiselTypeOf(bundleB))
}
-class Bar extends RawModule {
- val foo = Module(new Foo(new MyBundle()))
-}
+ChiselStage.emitVerilog(new Foo(new MyBundle))
```
### How do I create a Vec of Bools from a UInt?