2 files changed, 25 insertions, 3 deletions
diff --git a/AbstractModule.scala b/AbstractModule.scala
new file mode 100644
index 00000000..2c2574ad
--- /dev/null
+++ b/AbstractModule.scala
@@ -0,0 +1,21 @@
+package chiselTests
+
+import chisel3._
+import chisel3.stage.ChiselStage
+
+class AbstractModule[T <: Data](params: T) extends Module[T] {
+  val node = IO(params)
+}
+
+class AbstractModuleContainer extends Module {
+  val mod1 = Module(new AbstractModule[UInt](Input(UInt(0.W))))
+  val mod2 = Module(new AbstractModule[UInt](Output(UInt(0.W))))
+  mod2.node := mod1.node
+}
+
+object main {
+  def main(args: Array[String]): Unit = {
+    // println(getVerilogString(new Example))
+    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
+  }
+}
diff --git a/src/test/scala/chiselTests/AbstractModule.scala b/src/test/scala/chiselTests/AbstractModule.scala
index dc381120..9942f290 100644
--- a/src/test/scala/chiselTests/AbstractModule.scala
+++ b/src/test/scala/chiselTests/AbstractModule.scala
@@ -13,8 +13,9 @@ class AbstractModuleContainer extends Module {
   mod2.node := mod1.node
 }
 
-class AbstractModuleSpec extends ChiselPropSpec with Utils {
-  property("Abstract module should elaborate") {
-    ChiselStage.elaborate { new AbstractModuleContainer }
+object AbstractModuleSpec {
+  def main(args: Array[String]): Unit = {
+    // println(getVerilogString(new Example))
+    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
   }
 }