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| -rw-r--r-- | log.org | 14 |
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@@ -27,3 +27,17 @@ to get =AbstractInterface[A] => AbstractInterface[B] => AbstractInterface[C]= to work. - Next step will to be figure out multiple arities for =AbstractInterface= +* [2024-03-07 Thu] realization +- key realization this morning: there's a problematic muddling of two + separate things in chisel: the /content of the module body/ and + /scala-time computations/ +- verilog module bodies need to be simple, + post-scala-computation-representations of what computations actually + need to be in hardware. +** consequences of this problem at sifive +- diplomacy creates multiple levels of scala-time computations while + abstracting away the module body. + - lazymodule is the scala-time computation, lazymoduleimp is the verilog body +- people need to insert shit into bodies of "modules" using InModuleBody +- interface of resulting modules is indeterminable + |