diff options
| -rw-r--r-- | core/src/main/scala/chisel3/Mem.scala | 19 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 8 |
2 files changed, 14 insertions, 13 deletions
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala index d6ab9c4b..91872979 100644 --- a/core/src/main/scala/chisel3/Mem.scala +++ b/core/src/main/scala/chisel3/Mem.scala @@ -60,7 +60,10 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) // ensure memory ports are created with the same clock unless explicitly specified to use a different clock private val clockInst: Option[Clock] = Builder.currentClock - protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = { + // Only kept for binary compatibility reasons, impossible for users to call + protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = clockWarning(sourceInfo, MemPortDirection.INFER) + + protected def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit = { // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace val infoStr = sourceInfo.collect { case SourceLine(file, line, col) => s"$file:$line:$col" } Builder.deprecated( @@ -135,7 +138,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) compileOptions: CompileOptions ): T = { if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(Some(sourceInfo)) + clockWarning(Some(sourceInfo), dir) } makePort(sourceInfo, idx, dir, clock) } @@ -167,7 +170,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) implicit compileOptions: CompileOptions ): Unit = { if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(None) + clockWarning(None, MemPortDirection.WRITE) } implicit val sourceInfo = UnlocatableSourceInfo makePort(UnlocatableSourceInfo, idx, MemPortDirection.WRITE, clock) := data @@ -226,7 +229,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) ): Unit = { implicit val sourceInfo = UnlocatableSourceInfo if (warn && clockInst.isDefined && clock != clockInst.get) { - clockWarning(None) + clockWarning(None, MemPortDirection.WRITE) } val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]] val dataVec = data.asInstanceOf[Vec[Data]] @@ -274,7 +277,13 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) * @note when multiple conflicting writes are performed on a Mem element, the * result is undefined (unlike Vec, where the last assignment wins) */ -sealed class Mem[T <: Data] private[chisel3] (t: T, length: BigInt) extends MemBase(t, length) +sealed class Mem[T <: Data] private[chisel3] (t: T, length: BigInt) extends MemBase(t, length) { + override protected def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit = { + // Do not issue clock warnings on reads, since they are not clocked + if (dir != MemPortDirection.READ) + super.clockWarning(sourceInfo, dir) + } +} object SyncReadMem { diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 381b4009..29ec6509 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -166,14 +166,6 @@ class MultiClockSpec extends ChiselFlatSpec with Utils { } "Differing clocks at memory and read accessor instantiation" should "warn" in { - class modMemReadDifferingClock extends Module { - val myClock = IO(Input(Clock())) - val mem = withClock(myClock) { Mem(4, UInt(8.W)) } - val readVal = mem.read(0.U) - } - val (logMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemReadDifferingClock)) - logMemReadDifferingClock should include("memory is different") - class modSyncReadMemReadDifferingClock extends Module { val myClock = IO(Input(Clock())) val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) } |