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authorAditya Naik2024-06-05 13:09:47 -0700
committerAditya Naik2024-06-05 13:09:47 -0700
commite9d996e2a4f27e194ce3503d3ea8d9651b3ac3c2 (patch)
tree6e3cfbabc9b4542356843b8512946b4a0f8efde3 /src
parentc60561c8e7c58939e53b5a955f646900139d9c67 (diff)
Readd ports that were deleted for testing
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/stage/phases/Elaborate.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
index 98993899..3d580443 100644
--- a/src/main/scala/chisel3/stage/phases/Elaborate.scala
+++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -45,9 +45,9 @@ class Elaborate extends Phase {
/* if any throwable comes back and we're in "stack trace trimming" mode, then print an error and trim the stack trace
*/
case scala.util.control.NonFatal(a) =>
- if (!chiselOptions.printFullStackTrace) {
- a.trimStackTraceToUserCode()
- }
+ // if (!chiselOptions.printFullStackTrace) {
+ // a.trimStackTraceToUserCode()
+ // }
throw (a)
}
case a => Some(a)