Merge branch 'master' into add-asbool-to-clock

3 files changed, 21 insertions, 4 deletions

diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 612cdcc7..390f82a5 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -80,8 +80,11 @@ object Select {
     */
   def instances(module: BaseModule): Seq[BaseModule] = {
     check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case i: DefInstance => i.id
+    module._component.get match {
+      case d: DefModule => d.commands.collect {
+        case i: DefInstance => i.id
+      }
+      case other => Nil
     }
   }
 
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 0a0cc47c..df23f97d 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -16,7 +16,7 @@ import java.io.{StringWriter, PrintWriter}
 class ChiselStage extends Stage with PreservesAll[Phase] {
   val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli
 
-  val targets =
+  val targets: Seq[PhaseManager.PhaseDependency] =
     Seq( classOf[chisel3.stage.phases.Checks],
          classOf[chisel3.stage.phases.Elaborate],
          classOf[chisel3.stage.phases.AddImplicitOutputFile],
diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala
index f3c756ab..80ab518f 100644
--- a/src/test/scala/chiselTests/aop/SelectSpec.scala
+++ b/src/test/scala/chiselTests/aop/SelectSpec.scala
@@ -7,7 +7,9 @@ import chiselTests.ChiselFlatSpec
 import chisel3._
 import chisel3.aop.Select.{PredicatedConnect, When, WhenNot}
 import chisel3.aop.{Aspect, Select}
-import firrtl.{AnnotationSeq}
+import chisel3.experimental.ExtModule
+import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation}
+import firrtl.AnnotationSeq
 
 import scala.reflect.runtime.universe.TypeTag
 
@@ -139,5 +141,17 @@ class SelectSpec extends ChiselFlatSpec {
     )
   }
 
+  "Blackboxes" should "be supported in Select.instances" in {
+    class BB extends ExtModule { }
+    class Top extends RawModule {
+      val bb = Module(new BB)
+    }
+    val top = ChiselGeneratorAnnotation(() => {
+      new Top()
+    }).elaborate(1).asInstanceOf[DesignAnnotation[Top]].design
+    val bbs = Select.collectDeep(top) { case b: BB => b }
+    assert(bbs.size == 1)
+  }
+
 }