diff options
| author | Jack Koenig | 2021-01-19 15:54:49 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-19 15:54:49 -0800 |
| commit | cdb7bb27bd675a8a114701b97a45c56e26ef42b5 (patch) | |
| tree | c60b6b87501ba3fba0a70130905611cd512e5e43 /src/test | |
| parent | e94d41fc779e4e6b0b957a85da23532f23c45948 (diff) | |
Add when.cond for getting the current when condition (#1694)
This is useful for libraries to guard operations implemented via
annotations or BlackBoxes by the current when predicate
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/When.scala | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index b77c1f13..3b5ec62e 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -92,6 +92,42 @@ class SubmoduleWhenTester extends BasicTester { } } +class WhenCondTester extends BasicTester { + val pred = Wire(Vec(4, Bool())) + val (cycle, done) = Counter(true.B, 1 << pred.size) + // Cycle through every predicate + pred := cycle.asBools + val Seq(a, b, c, d) = pred // Just for nicer accessors + // When want the when predicates on connection to optimize away, + // it's not necessary but it makes the Verilog prettier + val w1, w2, w3, w4, w5, w6, w7 = WireInit(Bool(), DontCare) + when (a) { + w1 := when.cond + when (b) { + w2 := when.cond + }.elsewhen (c) { + w3 := when.cond + }.elsewhen (d) { + w4 := when.cond + }.otherwise { + w5 := when.cond + } + }.otherwise { + w6 := when.cond + } + w7 := when.cond + + assert(w1 === a) + assert(w2 === (a && b)) + assert(w3 === (a && !b && c)) + assert(w4 === (a && !b && !c && d)) + assert(w5 === (a && !b && !c && !d)) + assert(w6 === !a) + assert(w7) + + when (done) { stop() } +} + class WhenSpec extends ChiselFlatSpec with Utils { "When, elsewhen, and otherwise with orthogonal conditions" should "work" in { assertTesterPasses{ new WhenTester } @@ -105,6 +141,9 @@ class WhenSpec extends ChiselFlatSpec with Utils { "Conditional connections to submodule ports" should "be handled properly" in { assertTesterPasses(new SubmoduleWhenTester) } + "when.cond" should "give the current when condition" in { + assertTesterPasses(new WhenCondTester) + } "Returning in a when scope" should "give a reasonable error message" in { val e = the [ChiselException] thrownBy extractCause[ChiselException] { |
