summaryrefslogtreecommitdiff
path: root/src/test
diff options
context:
space:
mode:
authormergify[bot]2023-01-10 07:19:45 +0000
committerGitHub2023-01-10 07:19:45 +0000
commit9a7945fd86fcad02da0556d8f4a30daa4b005f9d (patch)
treedd8494fd69199cd9ac3be666987ab7afbeb643b4 /src/test
parent12785c6b2b8e378a5aa9db1833df7486d8f2a486 (diff)
Check for Vec subaccess in NamedComponent and throw a nicer error. (backport #2907) (#2928)
* Check for Vec subaccess in NamedComponent and throw a nicer error. (#2907) This would previously end up throwing an exception later, when trying to create a component name and realizing that it was invalid. Instead, this detects Vec subaccesses early, and gives a more precise error and suggestion. (cherry picked from commit d8c30961c7b293ee19024a487698630367ee71c6) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Resolve backport conflicts Co-authored-by: Mike Urbach <mikeurbach@gmail.com>
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/chiselTests/VecToTargetSpec.scala86
1 files changed, 86 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/VecToTargetSpec.scala b/src/test/scala/chiselTests/VecToTargetSpec.scala
new file mode 100644
index 00000000..20c6f306
--- /dev/null
+++ b/src/test/scala/chiselTests/VecToTargetSpec.scala
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+
+import chisel3._
+import chisel3.stage.ChiselStage
+
+trait VecToTargetSpecUtils extends Utils {
+ this: ChiselFunSpec =>
+
+ class Foo extends RawModule {
+ val vec = IO(Input(Vec(4, Bool())))
+
+ // Index a Vec with a Scala literal.
+ val scalaLit = 0
+ val vecSubaccessScalaLit = vec(scalaLit)
+
+ // Index a Vec with a Chisel literal.
+ val chiselLit = 0.U
+ val vecSubaccessChiselLit = vec(chiselLit)
+
+ // Index a Vec with a node.
+ val node = IO(Input(UInt(2.W)))
+ val vecSubaccessNode = vec(node)
+
+ // Put an otherwise un-targetable Vec subaccess into a temp.
+ val vecSubaccessTmp = WireInit(vecSubaccessNode)
+ }
+
+ val expectedError = "You cannot target Vec subaccess:"
+
+ def conversionSucceeds(data: InstanceId) = {
+ describe(".toTarget") {
+ it("should convert successfully") {
+ data.toTarget
+ }
+ }
+
+ describe(".toNamed") {
+ it("should convert successfully") {
+ data.toNamed
+ }
+ }
+ }
+
+ def conversionFails(data: InstanceId) = {
+ describe(".toTarget") {
+ it("should fail to convert with a useful error message") {
+ (the[ChiselException] thrownBy extractCause[ChiselException] {
+ data.toTarget
+ }).getMessage should include(expectedError)
+ }
+ }
+
+ describe(".toNamed") {
+ it("should fail to convert with a useful error message") {
+ (the[ChiselException] thrownBy extractCause[ChiselException] {
+ data.toNamed
+ }).getMessage should include(expectedError)
+ }
+ }
+ }
+}
+
+class VecToTargetSpec extends ChiselFunSpec with VecToTargetSpecUtils {
+ describe("Vec subaccess") {
+ var foo: Foo = null
+ ChiselStage.elaborate { foo = new Foo; foo }
+
+ describe("with a Scala literal") {
+ (it should behave).like(conversionSucceeds(foo.vecSubaccessScalaLit))
+ }
+
+ describe("with a Chisel literal") {
+ (it should behave).like(conversionFails(foo.vecSubaccessChiselLit))
+ }
+
+ describe("with a Node") {
+ (it should behave).like(conversionFails(foo.vecSubaccessNode))
+ }
+
+ describe("with an un-targetable construct that is assigned to a temporary") {
+ (it should behave).like(conversionSucceeds(foo.vecSubaccessTmp))
+ }
+ }
+}