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| author | Jiuyang Liu | 2021-04-30 05:12:24 +0000 |
|---|---|---|
| committer | GitHub | 2021-04-30 05:12:24 +0000 |
| commit | 7dd2d7db355d8dd9e1fc49ed7cd479ce5273b691 (patch) | |
| tree | 30193cdf9f1f0700cf465ca88e89efc61a4fea94 /src/test | |
| parent | c5861176887bfa529277e686df09a42aeceb6cd7 (diff) | |
add helper function to convert chirrtl to firrtl. (#1854)
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl.
* add scaladoc.
* add test.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/stage/ChiselStageSpec.scala | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala index 167e414b..7b6a2d39 100644 --- a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala +++ b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala @@ -88,6 +88,13 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { catchWrites { ChiselStage.convert(new Foo) } shouldBe a[Right[_, _]] } + ignore should "generate a FIRRTL circuit from a CHIRRTL circuit" in { + info("no files were written") + catchWrites { + ChiselStage.convert(ChiselStage.elaborate(new Foo)) + } shouldBe a[Right[_, _]] + } + behavior of "ChiselStage$.emitChirrtl" ignore should "generate a CHIRRTL string from a Chisel module" in { |