diff options
| author | Aditya Naik | 2023-12-15 09:22:44 -0800 |
|---|---|---|
| committer | Aditya Naik | 2023-12-15 09:22:44 -0800 |
| commit | 783bcb8b3436e342a04169eaf967db2dbc58abc7 (patch) | |
| tree | 7e67f79fa4e5d6662d5be696f86403bed677398d /src/test | |
| parent | af415532cf160e63e971ceb301833b8433c18a50 (diff) | |
Add abstract module
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/AbstractModule.scala | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/AbstractModule.scala b/src/test/scala/chiselTests/AbstractModule.scala index dc381120..9942f290 100644 --- a/src/test/scala/chiselTests/AbstractModule.scala +++ b/src/test/scala/chiselTests/AbstractModule.scala @@ -13,8 +13,9 @@ class AbstractModuleContainer extends Module { mod2.node := mod1.node } -class AbstractModuleSpec extends ChiselPropSpec with Utils { - property("Abstract module should elaborate") { - ChiselStage.elaborate { new AbstractModuleContainer } +object AbstractModuleSpec { + def main(args: Array[String]): Unit = { + // println(getVerilogString(new Example)) + println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer)) } } |
