Remove incorrect clock warning on Mem.read (backport #2721) (#2722)

* Remove incorrect clock warning on Mem.read (#2721)

Mem.read is combinational and thus unaffected by the clock, and so it
does not make sense to issue warnings about the current clock in this
context.

(cherry picked from commit 5fdf74f95e64cb69d6097547f20d789a83dbd735)

* Keep old version of MemBase.clockWarning for binary compatibility

This method is impossible for users to call, but it is easy enough to
keep around a version of it to make MiMa happy.

Co-authored-by: Andrew Waterman <andrew@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

1 files changed, 0 insertions, 8 deletions

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 381b4009..29ec6509 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -166,14 +166,6 @@ class MultiClockSpec extends ChiselFlatSpec with Utils {
   }
 
   "Differing clocks at memory and read accessor instantiation" should "warn" in {
-    class modMemReadDifferingClock extends Module {
-      val myClock = IO(Input(Clock()))
-      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
-      val readVal = mem.read(0.U)
-    }
-    val (logMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemReadDifferingClock))
-    logMemReadDifferingClock should include("memory is different")
-
     class modSyncReadMemReadDifferingClock extends Module {
       val myClock = IO(Input(Clock()))
       val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }