diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/cookbook/RegOfVec.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/cookbook/RegOfVec.scala')
| -rw-r--r-- | src/test/scala/cookbook/RegOfVec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala index 3e55acff..ba784871 100644 --- a/src/test/scala/cookbook/RegOfVec.scala +++ b/src/test/scala/cookbook/RegOfVec.scala @@ -19,7 +19,7 @@ class RegOfVec extends CookbookTester(2) { // Note that Seq.fill constructs 4 32-bit UInt literals with the value 0 // Vec(...) then constructs a Wire of these literals // The Reg is then initialized to the value of the Wire (which gives it the same type) - val initRegOfVec = Reg(init = Vec(Seq.fill(4)(0.asUInt(32.W)))) + val initRegOfVec = RegInit(Vec(Seq.fill(4)(0.U(32.W)))) // Simple test (cycle comes from superclass) when (cycle === 2.U) { assert(regOfVec(2) === 123.U) } |
