diff options
| author | Aditya Naik | 2023-11-23 03:11:56 -0800 |
|---|---|---|
| committer | Aditya Naik | 2023-11-23 03:11:56 -0800 |
| commit | af415532cf160e63e971ceb301833b8433c18a50 (patch) | |
| tree | 1fef70139846f57298c8e24a590490a74249f7dd /src/test/scala/cookbook/RegOfVec.scala | |
| parent | 8200c0cdf1d471453946d5ae24bc99757b2ef02d (diff) | |
cleanup
Diffstat (limited to 'src/test/scala/cookbook/RegOfVec.scala')
| -rw-r--r-- | src/test/scala/cookbook/RegOfVec.scala | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/src/test/scala/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala deleted file mode 100644 index ddb615c7..00000000 --- a/src/test/scala/cookbook/RegOfVec.scala +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package cookbook - -import chisel3._ - -/* ### How do I create a Reg of type Vec? - * - * For information, please see the API documentation for Vec - * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.Vec) - */ -class RegOfVec extends CookbookTester(2) { - // Reg of Vec of 32-bit UInts without initialization - val regOfVec = Reg(Vec(4, UInt(32.W))) - regOfVec(0) := 123.U // a couple of assignments - regOfVec(2) := regOfVec(0) - - // Reg of Vec of 32-bit UInts initialized to zero - // Note that Seq.fill constructs 4 32-bit UInt literals with the value 0 - // Vec(...) then constructs a Wire of these literals - // The Reg is then initialized to the value of the Wire (which gives it the same type) - val initRegOfVec = RegInit(VecInit(Seq.fill(4)(0.U(32.W)))) - - // Simple test (cycle comes from superclass) - when(cycle === 2.U) { assert(regOfVec(2) === 123.U) } - for (elt <- initRegOfVec) { assert(elt === 0.U) } -} - -class RegOfVecSpec extends CookbookSpec { - "RegOfVec" should "work" in { - assertTesterPasses { new RegOfVec } - } -} |
