cleanup

8 files changed, 0 insertions, 835 deletions

diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
deleted file mode 100644
index 38ffc3ba..00000000
--- a/src/test/scala/chiselTests/util/BitPatSpec.scala
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util
-
-import chisel3.util.BitPat
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
-
-class BitPatSpec extends AnyFlatSpec with Matchers {
-  behavior.of(classOf[BitPat].toString)
-
-  it should "convert a BitPat to readable form" in {
-    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-    BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
-  }
-
-  it should "convert a BitPat to raw form" in {
-    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-    BitPat("b" + testPattern).rawString should be(testPattern)
-  }
-
-  it should "not fail if BitPat width is 0" in {
-    intercept[IllegalArgumentException] { BitPat("b") }
-  }
-
-  it should "concat BitPat via ##" in {
-    (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
-  }
-
-  it should "throw when BitPat apply to a Hardware" in {
-    intercept[java.lang.IllegalArgumentException] {
-      chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module {
-        BitPat(chisel3.Reg(chisel3.Bool()))
-      })
-    }
-  }
-
-  it should "index and return new BitPat" in {
-    val b = BitPat("b1001???")
-    b(0) should be(BitPat.dontCare(1))
-    b(6) should be(BitPat.Y())
-    b(5) should be(BitPat.N())
-  }
-
-  it should "slice and return new BitPat" in {
-    val b = BitPat("b1001???")
-    b(2, 0) should be(BitPat("b???"))
-    b(4, 3) should be(BitPat("b01"))
-    b(6, 6) should be(BitPat("b1"))
-  }
-}
diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
deleted file mode 100644
index cf5f54cf..00000000
--- a/src/test/scala/chiselTests/util/BitSetSpec.scala
+++ /dev/null
@@ -1,145 +0,0 @@
-package chiselTests.util
-
-import chisel3.util.experimental.BitSet
-import chisel3.util.BitPat
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
-
-class BitSetSpec extends AnyFlatSpec with Matchers {
-  behavior.of(classOf[BitSet].toString)
-
-  it should "reject unequal width when constructing a BitSet" in {
-    intercept[IllegalArgumentException] {
-      BitSet.fromString("""b0010
-                          |b00010
-                          |""".stripMargin)
-    }
-  }
-
-  it should "return empty subtraction result correctly" in {
-    val aBitPat = BitPat("b10?")
-    val bBitPat = BitPat("b1??")
-
-    aBitPat.subtract(bBitPat).isEmpty should be(true)
-  }
-
-  it should "return nonempty subtraction result correctly" in {
-    val aBitPat = BitPat("b10?")
-    val bBitPat = BitPat("b1??")
-    val cBitPat = BitPat("b11?")
-    val dBitPat = BitPat("b100")
-
-    val diffBitPat = bBitPat.subtract(aBitPat)
-    bBitPat.cover(diffBitPat) should be(true)
-    diffBitPat.equals(cBitPat) should be(true)
-
-    val largerdiffBitPat = bBitPat.subtract(dBitPat)
-    aBitPat.cover(dBitPat) should be(true)
-    largerdiffBitPat.cover(diffBitPat) should be(true)
-  }
-
-  it should "be able to handle complex subtract between BitSet" in {
-    val aBitSet = BitSet.fromString("""b?01?0
-                                      |b11111
-                                      |b00000
-                                      |""".stripMargin)
-    val bBitSet = BitSet.fromString(
-      """b?1111
-        |b?0000
-        |""".stripMargin
-    )
-    val expected = BitPat("b?01?0")
-
-    expected.equals(aBitSet.subtract(bBitSet)) should be(true)
-  }
-
-  it should "be generated from BitPat union" in {
-    val aBitSet = BitSet.fromString("""b001?0
-                                      |b000??""".stripMargin)
-    val aBitPat = BitPat("b000??")
-    val bBitPat = BitPat("b001?0")
-    val cBitPat = BitPat("b00000")
-    aBitPat.cover(cBitPat) should be(true)
-    aBitSet.cover(bBitPat) should be(true)
-
-    aBitSet.equals(aBitPat.union(bBitPat)) should be(true)
-  }
-
-  it should "be generated from BitPat subtraction" in {
-    val aBitSet = BitSet.fromString("""b001?0
-                                      |b000??""".stripMargin)
-    val aBitPat = BitPat("b00???")
-    val bBitPat = BitPat("b001?1")
-
-    aBitSet.equals(aBitPat.subtract(bBitPat)) should be(true)
-  }
-
-  it should "union two BitSet together" in {
-    val aBitSet = BitSet.fromString("""b001?0
-                                      |b001?1
-                                      |""".stripMargin)
-    val bBitSet = BitSet.fromString(
-      """b000??
-        |b01???
-        |""".stripMargin
-    )
-    val cBitPat = BitPat("b0????")
-    cBitPat.equals(aBitSet.union(bBitSet)) should be(true)
-  }
-
-  it should "be decoded" in {
-    import chisel3._
-    import chisel3.util.experimental.decode.decoder
-    // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255]
-    // "0011????" "10??????" is empty to error
-    chisel3.stage.ChiselStage.emitSystemVerilog(new Module {
-      val in = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(4.W)))
-      out := decoder.bitset(
-        in,
-        Seq(
-          BitSet.fromString(
-            "b000?????"
-          ),
-          BitSet.fromString(
-            """b0010????
-              |b01??????
-              |""".stripMargin
-          ),
-          BitSet.fromString(
-            "b11??????"
-          )
-        ),
-        errorBit = true
-      )
-    })
-  }
-
-  it should "be decoded with DontCare error" in {
-    import chisel3._
-    import chisel3.util.experimental.decode.decoder
-    // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255]
-    // "0011????" "10??????" is empty to error
-    chisel3.stage.ChiselStage.emitSystemVerilog(new Module {
-      val in = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(4.W)))
-      out := decoder.bitset(
-        in,
-        Seq(
-          BitSet.fromString(
-            "b000?????"
-          ),
-          BitSet.fromString(
-            """b0010????
-              |b01??????
-              |""".stripMargin
-          ),
-          BitSet.fromString(
-            "b11??????"
-          )
-        ),
-        errorBit = false
-      )
-    })
-  }
-}
diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
deleted file mode 100644
index a75c4ec0..00000000
--- a/src/test/scala/chiselTests/util/CatSpec.scala
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.util.Cat
-import chisel3.experimental.noPrefix
-
-import chiselTests.ChiselFlatSpec
-
-object CatSpec {
-
-  class JackIsATypeSystemGod extends Module {
-    val in = IO(Input(Vec(0, UInt(8.W))))
-    val out = IO(Output(UInt(8.W)))
-
-    out := Cat(in)
-  }
-
-}
-
-class CatSpec extends ChiselFlatSpec {
-
-  import CatSpec._
-
-  behavior.of("util.Cat")
-
-  it should "not fail to elaborate a zero-element Vec" in {
-
-    ChiselStage.elaborate(new JackIsATypeSystemGod)
-
-  }
-
-  it should "not override the names of its arguments" in {
-    class MyModule extends RawModule {
-      val a, b, c, d = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt()))
-
-      out := Cat(a, b, c, d)
-    }
-    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    for (name <- Seq("a", "b", "c", "d")) {
-      chirrtl should include(s"input $name : UInt<8>")
-    }
-  }
-
-  it should "have prefixed naming" in {
-    class MyModule extends RawModule {
-      val in = IO(Input(Vec(8, UInt(8.W))))
-      val out = IO(Output(UInt()))
-
-      // noPrefix to avoid `out` as prefix
-      out := noPrefix(Cat(in))
-    }
-    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include("node lo_lo = cat(in[6], in[7])")
-    chirrtl should include("node lo_hi = cat(in[4], in[5])")
-    chirrtl should include("node hi_lo = cat(in[2], in[3])")
-    chirrtl should include("node hi_hi = cat(in[0], in[1])")
-  }
-
-}
diff --git a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala
deleted file mode 100644
index 32cf2431..00000000
--- a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util
-
-import chisel3._
-import chisel3.util.{is, switch, Counter, PriorityMux}
-import chisel3.testers.BasicTester
-import chisel3.stage.ChiselStage.emitChirrtl
-
-import chiselTests.ChiselFlatSpec
-
-class PriorityMuxTester extends BasicTester {
-
-  val sel = Wire(UInt(3.W))
-  sel := 0.U // default
-
-  val elts = Seq(5.U, 6.U, 7.U)
-  val muxed = PriorityMux(sel, elts)
-
-  // Priority is given to lowest order bit
-  val tests = Seq(
-    1.U -> elts(0),
-    2.U -> elts(1),
-    3.U -> elts(0),
-    4.U -> elts(2),
-    5.U -> elts(0),
-    6.U -> elts(1),
-    7.U -> elts(0)
-  )
-  val (cycle, done) = Counter(0 until tests.size + 1)
-
-  for (((in, out), idx) <- tests.zipWithIndex) {
-    when(cycle === idx.U) {
-      sel := in
-      assert(muxed === out)
-    }
-  }
-
-  when(done) {
-    stop()
-  }
-}
-
-class PriorityMuxSpec extends ChiselFlatSpec {
-  behavior.of("PriorityMux")
-
-  it should "be functionally correct" in {
-    assertTesterPasses(new PriorityMuxTester)
-  }
-
-  it should "be stack safe" in {
-    emitChirrtl(new RawModule {
-      val n = 1 << 15
-      val in = IO(Input(Vec(n, UInt(8.W))))
-      val sel = IO(Input(UInt(n.W)))
-      val out = IO(Output(UInt(8.W)))
-      out := PriorityMux(sel, in)
-    })
-  }
-}
diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
deleted file mode 100644
index 156249a2..00000000
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ /dev/null
@@ -1,111 +0,0 @@
-package chiselTests.util.experimental
-
-import chisel3._
-import chisel3.stage.PrintFullStackTraceAnnotation
-import chisel3.testers.BasicTester
-import chisel3.util.{pla, BitPat}
-import chiselTests.ChiselFlatSpec
-
-class PlaSpec extends ChiselFlatSpec {
-  "A 1-of-8 decoder (eg. 74xx138 without enables)" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b00000001")),
-        (BitPat("b001"), BitPat("b00000010")),
-        (BitPat("b010"), BitPat("b00000100")),
-        (BitPat("b011"), BitPat("b00001000")),
-        (BitPat("b100"), BitPat("b00010000")),
-        (BitPat("b101"), BitPat("b00100000")),
-        (BitPat("b110"), BitPat("b01000000")),
-        (BitPat("b111"), BitPat("b10000000"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(
-            plaOut === o.value.U(8.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-
-  "An active-low 1-of-8 decoder (eg. inverted 74xx138 without enables)" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b00000001")),
-        (BitPat("b001"), BitPat("b00000010")),
-        (BitPat("b010"), BitPat("b00000100")),
-        (BitPat("b011"), BitPat("b00001000")),
-        (BitPat("b100"), BitPat("b00010000")),
-        (BitPat("b101"), BitPat("b00100000")),
-        (BitPat("b110"), BitPat("b01000000")),
-        (BitPat("b111"), BitPat("b10000000"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table, BitPat("b11111111"))
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(
-            plaOut === ~o.value.U(8.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-
-  "#2112" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b000"), BitPat("b?01")),
-        (BitPat("b111"), BitPat("b?01"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(3.W))
-          chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
-      }
-      stop()
-    })
-  }
-
-  "A simple PLA" should "be generated correctly" in {
-    assertTesterPasses(new BasicTester {
-      val table = Seq(
-        (BitPat("b0000"), BitPat("b1")),
-        (BitPat("b0001"), BitPat("b1")),
-        (BitPat("b0010"), BitPat("b0")),
-        (BitPat("b0011"), BitPat("b1")),
-        (BitPat("b0100"), BitPat("b1")),
-        (BitPat("b0101"), BitPat("b0")),
-        (BitPat("b0110"), BitPat("b0")),
-        (BitPat("b0111"), BitPat("b0")),
-        (BitPat("b1000"), BitPat("b0")),
-        (BitPat("b1001"), BitPat("b0")),
-        (BitPat("b1010"), BitPat("b1")),
-        (BitPat("b1011"), BitPat("b0")),
-        (BitPat("b1100"), BitPat("b0")),
-        (BitPat("b1101"), BitPat("b1")),
-        (BitPat("b1110"), BitPat("b1")),
-        (BitPat("b1111"), BitPat("b1"))
-      )
-      table.foreach {
-        case (i, o) =>
-          val (plaIn, plaOut) = pla(table)
-          plaIn := WireDefault(i.value.U(4.W))
-          chisel3.assert(
-            plaOut === o.value.U(1.W),
-            "Input " + i.toString + " produced incorrect output BitPat(%b)",
-            plaOut
-          )
-      }
-      stop()
-    })
-  }
-}
diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
deleted file mode 100644
index b5dcee6b..00000000
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ /dev/null
@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental
-
-import chisel3._
-import chisel3.util.BitPat
-import chisel3.util.experimental.decode.{decoder, TruthTable}
-import org.scalatest.flatspec.AnyFlatSpec
-
-class TruthTableSpec extends AnyFlatSpec {
-  val table = TruthTable(
-    Map(
-      // BitPat("b000") -> BitPat("b0"),
-      BitPat("b001") -> BitPat("b?"),
-      BitPat("b010") -> BitPat("b?"),
-      // BitPat("b011") -> BitPat("b0"),
-      BitPat("b100") -> BitPat("b1"),
-      BitPat("b101") -> BitPat("b1"),
-      // BitPat("b110") -> BitPat("b0"),
-      BitPat("b111") -> BitPat("b1")
-    ),
-    BitPat("b0")
-  )
-  val str = """001->?
-              |010->?
-              |100->1
-              |101->1
-              |111->1
-              |0""".stripMargin
-  "TruthTable" should "serialize" in {
-    assert(table.toString contains "001->?")
-    assert(table.toString contains "010->?")
-    assert(table.toString contains "100->1")
-    assert(table.toString contains "111->1")
-    assert(table.toString contains "     0")
-  }
-  "TruthTable" should "deserialize" in {
-    val table2 = TruthTable.fromString(str)
-    assert(table2 === table)
-    assert(table2.hashCode === table.hashCode)
-  }
-  "TruthTable" should "merge same key" in {
-    assert(
-      TruthTable.fromString(
-        """001100->??1
-          |001100->1??
-          |???
-          |""".stripMargin
-      ) == TruthTable.fromString(
-        """001100->1?1
-          |???
-          |""".stripMargin
-      )
-    )
-  }
-  "TruthTable" should "crash when merging 0 and 1" in {
-    intercept[IllegalArgumentException] {
-      TruthTable.fromString(
-        """0->0
-          |0->1
-          |???
-          |""".stripMargin
-      )
-    }
-  }
-  "TruthTable" should "be reproducible" in {
-    class Foo extends Module {
-
-      val io = IO(new Bundle {
-        val in = Input(UInt(4.W))
-        val out = Output(UInt(16.W))
-      })
-
-      val table = TruthTable(
-        (0 until 16).map { i =>
-          BitPat(i.U(4.W)) -> BitPat((1 << i).U(16.W))
-        },
-        BitPat.dontCare(16)
-      )
-
-      io.out := decoder.qmc(io.in, table)
-    }
-    assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo))
-  }
-  "TruthTable" should "accept unknown input width" in {
-    val t = TruthTable(
-      Seq(
-        BitPat(0.U) -> BitPat.dontCare(1),
-        BitPat(1.U) -> BitPat.dontCare(1),
-        BitPat(2.U) -> BitPat.dontCare(1),
-        BitPat(3.U) -> BitPat.dontCare(1),
-        BitPat(4.U) -> BitPat.dontCare(1),
-        BitPat(5.U) -> BitPat.dontCare(1),
-        BitPat(6.U) -> BitPat.dontCare(1),
-        BitPat(7.U) -> BitPat.dontCare(1)
-      ),
-      BitPat.N(1)
-    )
-    assert(t.toString contains "000->?")
-    assert(t.toString contains "001->?")
-    assert(t.toString contains "010->?")
-    assert(t.toString contains "011->?")
-    assert(t.toString contains "100->?")
-    assert(t.toString contains "101->?")
-    assert(t.toString contains "110->?")
-    assert(t.toString contains "111->?")
-    assert(t.toString contains "     0")
-  }
-
-  "Using TruthTable.fromEspressoOutput" should "merge rows on conflict" in {
-    val mapping = List(
-      (BitPat("b110"), BitPat("b001")),
-      (BitPat("b111"), BitPat("b001")),
-      (BitPat("b111"), BitPat("b010")),
-      (BitPat("b111"), BitPat("b100"))
-    )
-
-    assert(
-      TruthTable.fromEspressoOutput(mapping, BitPat("b?")) ==
-        TruthTable.fromString("""110->001
-                                |111->111
-                                |?
-                                |""".stripMargin)
-    )
-  }
-}
diff --git a/src/test/scala/chiselTests/util/random/LFSRSpec.scala b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
deleted file mode 100644
index d47c2d7d..00000000
--- a/src/test/scala/chiselTests/util/random/LFSRSpec.scala
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.random
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.util.{Cat, Counter, Enum}
-import chisel3.util.random._
-import chisel3.testers.{BasicTester, TesterDriver}
-import chiselTests.{ChiselFlatSpec, Utils}
-
-import math.pow
-
-class FooLFSR(val reduction: LFSRReduce, seed: Option[BigInt]) extends PRNG(4, seed) with LFSR {
-  def delta(s: Seq[Bool]): Seq[Bool] = s
-}
-
-class LFSRMaxPeriod(gen: => UInt) extends BasicTester {
-
-  val rv = gen
-  val started = RegNext(true.B, false.B)
-  val seed = withReset(!started) { RegInit(rv) }
-
-  val (_, wrap) = Counter(started, math.pow(2.0, rv.getWidth).toInt - 1)
-
-  when(rv === seed && started) {
-    chisel3.assert(wrap)
-    stop()
-  }
-
-  val last = RegNext(rv)
-  chisel3.assert(rv =/= last, "LFSR last value (0b%b) was equal to current value (0b%b)", rv, last)
-
-}
-
-/**
-  * This test creates two 4 sided dice.
-  * Each cycle it adds them together and adds a count to the bin corresponding to that value
-  * The asserts check that the bins show the correct distribution.
-  */
-class LFSRDistribution(gen: => UInt, cycles: Int = 10000) extends BasicTester {
-
-  val rv = gen
-  val bins = Reg(Vec(8, UInt(32.W)))
-
-  // Use tap points on each LFSR so values are more independent
-  val die0 = Cat(Seq.tabulate(2) { i => rv(i) })
-  val die1 = Cat(Seq.tabulate(2) { i => rv(i + 2) })
-
-  val (trial, done) = Counter(true.B, cycles)
-
-  val rollValue = die0 +& die1 // Note +& is critical because sum will need an extra bit.
-
-  bins(rollValue) := bins(rollValue) + 1.U
-
-  when(done) {
-    printf(p"bins: $bins\n") // Note using the printable interpolator p"" to print out a Vec
-
-    // test that the distribution feels right.
-    assert(bins(1) > bins(0))
-    assert(bins(2) > bins(1))
-    assert(bins(3) > bins(2))
-    assert(bins(4) < bins(3))
-    assert(bins(5) < bins(4))
-    assert(bins(6) < bins(5))
-    assert(bins(7) === 0.U)
-
-    stop()
-  }
-}
-
-/** This tests that after reset an LFSR is not locked up. This manually sets the seed of the LFSR at run-time to the
-  * value that would cause it to lock up. It then asserts reset. The next cycle it checks that the value is NOT the
-  * locked up value.
-  * @param gen an LFSR to test
-  * @param lockUpValue the value that would lock up the LFSR
-  */
-class LFSRResetTester(gen: => LFSR, lockUpValue: BigInt) extends BasicTester {
-
-  val lfsr = Module(gen)
-  lfsr.io.seed.valid := false.B
-  lfsr.io.seed.bits := DontCare
-  lfsr.io.increment := true.B
-
-  val (count, done) = Counter(true.B, 5)
-
-  lfsr.io.seed.valid := count === 1.U
-  lfsr.io.seed.bits := lockUpValue.U(lfsr.width.W).asBools
-  lfsr.io.increment := true.B
-
-  when(count === 2.U) {
-    assert(lfsr.io.out.asUInt === lockUpValue.U, "LFSR is NOT locked up, but should be!")
-  }
-
-  lfsr.reset := count === 3.U
-
-  when(count === 4.U) {
-    assert(lfsr.io.out.asUInt =/= lockUpValue.U, "LFSR is locked up, but should not be after reset!")
-  }
-
-  when(done) {
-    stop()
-  }
-
-}
-
-class LFSRSpec extends ChiselFlatSpec with Utils {
-
-  def periodCheck(gen: (Int, Set[Int], LFSRReduce) => PRNG, reduction: LFSRReduce, range: Range): Unit = {
-    val testName = s"have a maximal period over a range of widths (${range.head} to ${range.last})" +
-      s" using ${reduction.getClass}"
-    it should testName in {
-      range.foreach { width =>
-        LFSR.tapsMaxPeriod(width).foreach { taps =>
-          info(s"""width $width okay using taps: ${taps.mkString(", ")}""")
-          assertTesterPasses(
-            new LFSRMaxPeriod(PRNG(gen(width, taps, reduction))),
-            annotations = TesterDriver.verilatorOnly
-          )
-        }
-      }
-    }
-  }
-
-  behavior.of("LFSR")
-
-  it should "throw an exception if initialized to a seed of zero for XOR configuration" in {
-    {
-      the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] {
-        ChiselStage.elaborate(new FooLFSR(XOR, Some(0)))
-      }
-    }.getMessage should include("Seed cannot be zero")
-  }
-
-  it should "throw an exception if initialized to a seed of all ones for XNOR configuration" in {
-    {
-      the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] {
-        ChiselStage.elaborate(new FooLFSR(XNOR, Some(15)))
-      }
-    }.getMessage should include("Seed cannot be all ones")
-  }
-
-  it should "reset correctly without a seed for XOR configuration" in {
-    assertTesterPasses(new LFSRResetTester(new FooLFSR(XOR, None), 0))
-  }
-
-  it should "reset correctly without a seed for XNOR configuration" in {
-    assertTesterPasses(new LFSRResetTester(new FooLFSR(XNOR, None), 15))
-  }
-
-  behavior.of("MaximalPeriodGaloisLFSR")
-
-  it should "throw an exception if no LFSR taps are known" in {
-    {
-      the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] {
-        ChiselStage.elaborate(new MaxPeriodGaloisLFSR(787))
-      }
-    }.getMessage should include("No max period LFSR taps stored for requested width")
-  }
-
-  periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction = r), XOR, 2 to 16)
-  periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new GaloisLFSR(w, t, reduction = r), XNOR, 2 to 16)
-
-  ignore should "have a sane distribution for larger widths" in {
-    ((17 to 32) ++ Seq(64, 128, 256, 512, 1024, 2048, 4096)).foreach { width =>
-      info(s"width $width okay!")
-      assertTesterPasses(new LFSRDistribution(LFSR(width), math.pow(2, 22).toInt))
-    }
-  }
-
-  behavior.of("MaximalPeriodFibonacciLFSR")
-
-  periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction = r), XOR, 2 to 16)
-  periodCheck((w: Int, t: Set[Int], r: LFSRReduce) => new FibonacciLFSR(w, t, reduction = r), XNOR, 2 to 16)
-
-  behavior.of("LFSR maximal period taps")
-
-  it should "contain all the expected widths" in {
-    ((2 to 786) ++ Seq(1024, 2048, 4096)).foreach(LFSR.tapsMaxPeriod.keys should contain(_))
-  }
-
-}
diff --git a/src/test/scala/chiselTests/util/random/PRNGSpec.scala b/src/test/scala/chiselTests/util/random/PRNGSpec.scala
deleted file mode 100644
index 36fdf9cb..00000000
--- a/src/test/scala/chiselTests/util/random/PRNGSpec.scala
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.random
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.testers.BasicTester
-import chisel3.util.Counter
-import chisel3.util.random.PRNG
-
-import chiselTests.{ChiselFlatSpec, Utils}
-
-class CyclePRNG(width: Int, seed: Option[BigInt], step: Int, updateSeed: Boolean)
-    extends PRNG(width, seed, step, updateSeed) {
-
-  def delta(s: Seq[Bool]): Seq[Bool] = s.last +: s.dropRight(1)
-
-}
-
-class PRNGStepTest extends BasicTester {
-
-  val count2: UInt = Counter(true.B, 2)._1
-  val count4: UInt = Counter(true.B, 4)._1
-
-  val a: UInt = PRNG(new CyclePRNG(16, Some(1), 1, false), true.B)
-  val b: UInt = PRNG(new CyclePRNG(16, Some(1), 2, false), count2 === 1.U)
-  val c: UInt = PRNG(new CyclePRNG(16, Some(1), 4, false), count4 === 3.U)
-
-  val (_, done) = Counter(true.B, 16)
-
-  when(count2 === 0.U) {
-    assert(a === b, "1-step and 2-step PRNGs did not agree! (0b%b != 0b%b)", a, b)
-  }
-
-  when(count4 === 0.U) {
-    assert(a === c, "1-step and 4-step PRNGs did not agree!")
-  }
-
-  when(done) {
-    stop()
-  }
-
-}
-
-class PRNGUpdateSeedTest(updateSeed: Boolean, seed: BigInt, expected: BigInt) extends BasicTester {
-
-  val a: CyclePRNG = Module(new CyclePRNG(16, Some(1), 1, updateSeed))
-
-  val (count, done) = Counter(true.B, 4)
-
-  a.io.increment := true.B
-  a.io.seed.valid := count === 2.U
-  a.io.seed.bits := seed.U(a.width.W).asBools
-
-  when(count === 3.U) {
-    assert(a.io.out.asUInt === expected.U, "Output didn't match!")
-  }
-
-  when(done) {
-    stop()
-  }
-
-}
-
-class PRNGSpec extends ChiselFlatSpec with Utils {
-
-  behavior.of("PRNG")
-
-  it should "throw an exception if the step size is < 1" in {
-    {
-      the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] {
-        ChiselStage.elaborate(new CyclePRNG(0, Some(1), 1, true))
-      }
-    }.getMessage should include("Width must be greater than zero!")
-  }
-
-  it should "throw an exception if the step size is <= 0" in {
-    {
-      the[IllegalArgumentException] thrownBy extractCause[IllegalArgumentException] {
-        ChiselStage.elaborate(new CyclePRNG(1, Some(1), 0, true))
-      }
-    }.getMessage should include("Step size must be greater than one!")
-  }
-
-  it should "handle non-unary steps" in {
-    assertTesterPasses(new PRNGStepTest)
-  }
-
-  it should "handle state update without and with updateSeed enabled" in {
-    info("without updateSeed okay!")
-    assertTesterPasses(new PRNGUpdateSeedTest(false, 3, 3))
-
-    info("with updateSeed okay!")
-    assertTesterPasses(new PRNGUpdateSeedTest(true, 3, 6))
-  }
-
-}