cleanup

3 files changed, 0 insertions, 1073 deletions

diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
deleted file mode 100644
index a787bb80..00000000
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ /dev/null
@@ -1,362 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.naming
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.aop.Select
-import chisel3.experimental.{prefix, treedump}
-import chiselTests.{ChiselFlatSpec, Utils}
-
-class NamePluginSpec extends ChiselFlatSpec with Utils {
-  implicit val minimumScalaVersion: Int = 12
-
-  "Scala plugin" should "name internally scoped components" in {
-    class Test extends Module {
-      { val mywire = Wire(UInt(3.W)) }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).head.toTarget.ref should be("mywire")
-    }
-  }
-
-  "Scala plugin" should "name internally scoped instances" in {
-    class Inner extends Module {}
-    class Test extends Module {
-      { val myinstance = Module(new Inner) }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.instances(top).head.instanceName should be("myinstance")
-    }
-  }
-
-  "Scala plugin" should "interact with prefixing" in {
-    class Test extends Module {
-      def builder() = {
-        val wire = Wire(UInt(3.W))
-      }
-      prefix("first") {
-        builder()
-      }
-      prefix("second") {
-        builder()
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("first_wire", "second_wire"))
-    }
-  }
-
-  "Scala plugin" should "interact with prefixing so last val name wins" in {
-    class Test extends Module {
-      def builder() = {
-        val wire1 = Wire(UInt(3.W))
-        val wire2 = Wire(UInt(3.W))
-        wire2
-      }
-      {
-        val x1 = prefix("first") {
-          builder()
-        }
-      }
-      {
-        val x2 = prefix("second") {
-          builder()
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("x1_first_wire1", "x1", "x2_second_wire1", "x2"))
-    }
-  }
-
-  "Scala plugin" should "name verification ops" in {
-    class Test extends Module {
-      val foo, bar = IO(Input(UInt(8.W)))
-
-      {
-        val x1 = chisel3.assert(1.U === 1.U)
-        val x2 = cover(foo =/= bar)
-        val x3 = chisel3.assume(foo =/= 123.U)
-        val x4 = printf("foo = %d\n", foo)
-      }
-    }
-    val chirrtl = ChiselStage.emitChirrtl(new Test)
-    (chirrtl should include).regex("assert.*: x1")
-    (chirrtl should include).regex("cover.*: x2")
-    (chirrtl should include).regex("assume.*: x3")
-    (chirrtl should include).regex("printf.*: x4")
-  }
-
-  "Naming on option" should "work" in {
-
-    class Test extends Module {
-      def builder(): Option[UInt] = {
-        val a = Wire(UInt(3.W))
-        Some(a)
-      }
-
-      { val blah = builder() }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("blah"))
-    }
-  }
-
-  "Naming on iterables" should "work" in {
-
-    class Test extends Module {
-      def builder(): Seq[UInt] = {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        Seq(a, b)
-      }
-      {
-        val blah = {
-          builder()
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("blah_0", "blah_1"))
-    }
-  }
-
-  "Naming on nested iterables" should "work" in {
-
-    class Test extends Module {
-      def builder(): Seq[Seq[UInt]] = {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        val c = Wire(UInt(3.W))
-        val d = Wire(UInt(3.W))
-        Seq(Seq(a, b), Seq(c, d))
-      }
-      {
-        val blah = {
-          builder()
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(
-        List(
-          "blah_0_0",
-          "blah_0_1",
-          "blah_1_0",
-          "blah_1_1"
-        )
-      )
-    }
-  }
-
-  "Naming on custom case classes" should "not work" in {
-    case class Container(a: UInt, b: UInt)
-
-    class Test extends Module {
-      def builder(): Container = {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        Container(a, b)
-      }
-
-      { val blah = builder() }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a", "b"))
-    }
-  }
-
-  "Multiple names on an IO within a module" should "get the first name" in {
-    class Test extends RawModule {
-      {
-        val a = IO(Output(UInt(3.W)))
-        val b = a
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.ios(top).map(_.instanceName) should be(List("a"))
-    }
-  }
-
-  "Multiple names on a non-IO" should "get the first name" in {
-    class Test extends Module {
-      {
-        val a = Wire(UInt(3.W))
-        val b = a
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a"))
-    }
-  }
-
-  "Outer Expression, First Statement naming" should "apply to IO" in {
-    class Test extends RawModule {
-      {
-        val widthOpt: Option[Int] = Some(4)
-        val out = widthOpt.map { w =>
-          val port = IO(Output(UInt(w.W)))
-          port
-        }
-        val foo = out
-        val bar = out.get
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.ios(top).map(_.instanceName) should be(List("out"))
-    }
-  }
-
-  "Outer Expression, First Statement naming" should "apply to non-IO" in {
-    class Test extends RawModule {
-      {
-        val widthOpt: Option[Int] = Some(4)
-        val fizz = widthOpt.map { w =>
-          val wire = Wire(UInt(w.W))
-          wire
-        }
-        val foo = fizz
-        val bar = fizz.get
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("fizz"))
-    }
-  }
-
-  "autoSeed" should "NOT override automatic naming for IO" in {
-    class Test extends RawModule {
-      {
-        val a = IO(Output(UInt(3.W)))
-        a.autoSeed("b")
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.ios(top).map(_.instanceName) should be(List("a"))
-    }
-  }
-
-  "autoSeed" should "override automatic naming for non-IO" in {
-    class Test extends Module {
-      {
-        val a = Wire(UInt(3.W))
-        a.autoSeed("b")
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("b"))
-    }
-  }
-
-  "Unapply assignments" should "still be named" in {
-    class Test extends Module {
-      {
-        val (a, b) = (Wire(UInt(3.W)), Wire(UInt(3.W)))
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a", "b"))
-    }
-  }
-
-  "Unapply assignments" should "not override already named things" in {
-    class Test extends Module {
-      {
-        val x = Wire(UInt(3.W))
-        val (a, b) = (x, Wire(UInt(3.W)))
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("x", "b"))
-    }
-  }
-
-  "Case class unapply assignments" should "be named" in {
-    case class Foo(x: UInt, y: UInt)
-    class Test extends Module {
-      {
-        def func() = Foo(Wire(UInt(3.W)), Wire(UInt(3.W)))
-        val Foo(a, b) = func()
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a", "b"))
-    }
-  }
-
-  "Complex unapply assignments" should "be named" in {
-    case class Foo(x: UInt, y: UInt)
-    class Test extends Module {
-      {
-        val w = Wire(UInt(3.W))
-        def func() = {
-          val x = Foo(Wire(UInt(3.W)), Wire(UInt(3.W)))
-          (x, w) :: Nil
-        }
-        val ((Foo(a, _), c) :: Nil) = func()
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("w", "a", "_WIRE"))
-    }
-  }
-
-  "Recursive types" should "not infinitely loop" in {
-    // When this fails, it causes a StackOverflow when compiling the tests
-    // Unfortunately, this doesn't seem to work with assertCompiles(...), it probably ignores the
-    // custom project scalacOptions
-    def func(x: String) = {
-      // We only check types of vals, we don't actually want to run this code though
-      val y = scala.xml.XML.loadFile(x)
-      y
-    }
-  }
-
-  "Nested val declarations" should "all be named" in {
-    class Test extends Module {
-      {
-        val a = {
-          val b = {
-            val c = Wire(UInt(3.W))
-            Wire(UInt(3.W))
-          }
-          Wire(UInt(3.W))
-        }
-      }
-    }
-
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a_b_c", "a_b", "a"))
-    }
-  }
-
-  behavior.of("Unnamed values (aka \"Temporaries\")")
-
-  they should "be declared by starting the name with '_'" in {
-    class Test extends Module {
-      {
-        val a = {
-          val b = {
-            val _c = Wire(UInt(3.W))
-            4.U // literal so there is no name
-          }
-          b
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("_a_b_c"))
-    }
-  }
-}
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
deleted file mode 100644
index d8cb3348..00000000
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ /dev/null
@@ -1,550 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.naming
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.aop.Select
-import chisel3.experimental.{dump, noPrefix, prefix, treedump}
-import chiselTests.{ChiselPropSpec, Utils}
-import chisel3.experimental.AffectsChiselPrefix
-
-class PrefixSpec extends ChiselPropSpec with Utils {
-  implicit val minimumMajorVersion: Int = 12
-  property("Scala plugin should interact with prefixing so last plugin name wins?") {
-    class Test extends Module {
-      def builder(): UInt = {
-        val wire1 = Wire(UInt(3.W))
-        val wire2 = Wire(UInt(3.W))
-        wire2
-      }
-
-      {
-        val x1 = prefix("first") {
-          builder()
-        }
-      }
-      {
-        val x2 = prefix("second") {
-          builder()
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("x1_first_wire1", "x1", "x2_second_wire1", "x2"))
-    }
-  }
-
-  property("Nested prefixes should work") {
-    class Test extends Module {
-      def builder2(): UInt = {
-        val wire1 = Wire(UInt(3.W))
-        val wire2 = Wire(UInt(3.W))
-        wire2
-      }
-      def builder(): UInt = {
-        val wire1 = Wire(UInt(3.W))
-        val wire2 = Wire(UInt(3.W))
-        prefix("foo") {
-          builder2()
-        }
-      }
-      { val x1 = builder() }
-      { val x2 = builder() }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(
-        List(
-          "x1_wire1",
-          "x1_wire2",
-          "x1_foo_wire1",
-          "x1",
-          "x2_wire1",
-          "x2_wire2",
-          "x2_foo_wire1",
-          "x2"
-        )
-      )
-    }
-  }
-
-  property("Prefixing seeded with signal") {
-    class Test extends Module {
-      def builder(): UInt = {
-        val wire = Wire(UInt(3.W))
-        wire := 3.U
-        wire
-      }
-      {
-        val x1 = Wire(UInt(3.W))
-        x1 := {
-          builder()
-        }
-        val x2 = Wire(UInt(3.W))
-        x2 := {
-          builder()
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("x1", "x1_wire", "x2", "x2_wire"))
-    }
-  }
-
-  property("Automatic prefixing should work") {
-
-    class Test extends Module {
-      def builder(): UInt = {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        b
-      }
-
-      {
-        val ADAM = builder()
-        val JACOB = builder()
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("ADAM_a", "ADAM", "JACOB_a", "JACOB"))
-    }
-  }
-
-  property("No prefixing annotation on defs should work") {
-
-    class Test extends Module {
-      def builder(): UInt = noPrefix {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        b
-      }
-
-      { val noprefix = builder() }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a", "noprefix"))
-    }
-  }
-
-  property("Prefixing on temps should work") {
-
-    class Test extends Module {
-      def builder(): UInt = {
-        val a = Wire(UInt(3.W))
-        val b = Wire(UInt(3.W))
-        a +& (b * a)
-      }
-
-      { val blah = builder() }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.ops(top).map(x => (x._1, x._2.instanceName)) should be(
-        List(
-          ("mul", "_blah_T"),
-          ("add", "blah")
-        )
-      )
-    }
-  }
-
-  property("Prefixing should not leak into child modules") {
-    class Child extends Module {
-      {
-        val wire = Wire(UInt())
-      }
-    }
-
-    class Test extends Module {
-      {
-        val child = prefix("InTest") {
-          Module(new Child)
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(Select.instances(top).head).map(_.instanceName) should be(List("wire"))
-    }
-  }
-
-  property("Prefixing should not leak into child modules, example 2") {
-    class Child extends Module {
-      {
-        val wire = Wire(UInt())
-      }
-    }
-
-    class Test extends Module {
-      val x = IO(Input(UInt(3.W)))
-      val y = {
-        lazy val module = new Child
-        val child = Module(module)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(Select.instances(top).head).map(_.instanceName) should be(List("wire"))
-    }
-  }
-
-  property("Instance names should not be added to prefix") {
-    class Child(tpe: UInt) extends Module {
-      {
-        val io = IO(Input(tpe))
-      }
-    }
-
-    class Test extends Module {
-      {
-        lazy val module = {
-          val x = UInt(3.W)
-          new Child(x)
-        }
-        val child = Module(module)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.ios(Select.instances(top).head).map(_.instanceName) should be(List("clock", "reset", "io"))
-    }
-  }
-
-  property("Prefixing should not be caused by nested Iterable[Iterable[Any]]") {
-    class Test extends Module {
-      {
-        val iia = {
-          val wire = Wire(UInt(3.W))
-          List(List("Blah"))
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("wire"))
-    }
-  }
-
-  property("Prefixing should be caused by nested Iterable[Iterable[Data]]") {
-    class Test extends Module {
-      {
-        val iia = {
-          val wire = Wire(UInt(3.W))
-          List(List(3.U))
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("iia_wire"))
-    }
-  }
-
-  property("Prefixing should NOT be influenced by suggestName") {
-    class Test extends Module {
-      {
-        val wire = {
-          val x = Wire(UInt(3.W)) // wire_x
-          Wire(UInt(3.W)).suggestName("foo")
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("wire_x", "foo"))
-    }
-  }
-
-  property("Prefixing should be influenced by the \"current name\" of the signal") {
-    class Test extends Module {
-      {
-        val wire = {
-          val y = Wire(UInt(3.W)).suggestName("foo")
-          val x = Wire(UInt(3.W)) // wire_x
-          y
-        }
-
-        val wire2 = Wire(UInt(3.W))
-        wire2 := {
-          val x = Wire(UInt(3.W)) // wire2_x
-          x + 1.U
-        }
-        wire2.suggestName("bar")
-
-        val wire3 = Wire(UInt(3.W))
-        wire3.suggestName("fizz")
-        wire3 := {
-          val x = Wire(UInt(3.W)) // fizz_x
-          x + 1.U
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("foo", "wire_x", "bar", "wire2_x", "fizz", "fizz_x"))
-    }
-  }
-
-  property("Prefixing have intuitive behavior") {
-    class Test extends Module {
-      {
-        val wire = {
-          val x = Wire(UInt(3.W)).suggestName("mywire")
-          val y = Wire(UInt(3.W)).suggestName("mywire2")
-          y := x
-          y
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("wire_mywire", "mywire2"))
-    }
-  }
-
-  property("Prefixing on connection to subfields work") {
-    class Test extends Module {
-      {
-        val wire = Wire(new Bundle {
-          val x = UInt(3.W)
-          val y = UInt(3.W)
-          val vec = Vec(4, UInt(3.W))
-        })
-        wire.x := RegNext(3.U)
-        wire.y := RegNext(3.U)
-        wire.vec(0) := RegNext(3.U)
-        wire.vec(wire.x) := RegNext(3.U)
-        wire.vec(1.U) := RegNext(3.U)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.registers(top).map(_.instanceName) should be(
-        List(
-          "wire_x_REG",
-          "wire_y_REG",
-          "wire_vec_0_REG",
-          "wire_vec_REG",
-          "wire_vec_1_REG"
-        )
-      )
-    }
-  }
-
-  property("Prefixing on connection to IOs should work") {
-    class Child extends Module {
-      val in = IO(Input(UInt(3.W)))
-      val out = IO(Output(UInt(3.W)))
-      out := RegNext(in)
-    }
-    class Test extends Module {
-      {
-        val child = Module(new Child)
-        child.in := RegNext(3.U)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.registers(top).map(_.instanceName) should be(
-        List(
-          "child_in_REG"
-        )
-      )
-      Select.registers(Select.instances(top).head).map(_.instanceName) should be(
-        List(
-          "out_REG"
-        )
-      )
-    }
-  }
-
-  property("Prefixing on bulk connects should work") {
-    class Child extends Module {
-      val in = IO(Input(UInt(3.W)))
-      val out = IO(Output(UInt(3.W)))
-      out := RegNext(in)
-    }
-    class Test extends Module {
-      {
-        val child = Module(new Child)
-        child.in <> RegNext(3.U)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.registers(top).map(_.instanceName) should be(
-        List(
-          "child_in_REG"
-        )
-      )
-      Select.registers(Select.instances(top).head).map(_.instanceName) should be(
-        List(
-          "out_REG"
-        )
-      )
-    }
-  }
-
-  property("Connections should use the non-prefixed name of the connected Data") {
-    class Test extends Module {
-      prefix("foo") {
-        val x = Wire(UInt(8.W))
-        x := {
-          val w = Wire(UInt(8.W))
-          w := 3.U
-          w + 1.U
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("foo_x", "foo_x_w"))
-    }
-  }
-
-  property("Connections to aggregate fields should use the non-prefixed aggregate name") {
-    class Test extends Module {
-      prefix("foo") {
-        val x = Wire(new Bundle { val bar = UInt(8.W) })
-        x.bar := {
-          val w = Wire(new Bundle { val fizz = UInt(8.W) })
-          w.fizz := 3.U
-          w.fizz + 1.U
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("foo_x", "foo_x_bar_w"))
-    }
-  }
-
-  property("Prefixing with wires in recursive functions should grow linearly") {
-    class Test extends Module {
-      def func(bools: Seq[Bool]): Bool = {
-        if (bools.isEmpty) true.B
-        else {
-          val w = Wire(Bool())
-          w := bools.head && func(bools.tail)
-          w
-        }
-      }
-      val in = IO(Input(Vec(4, Bool())))
-      val x = func(in)
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("x", "x_w_w", "x_w_w_w", "x_w_w_w_w"))
-    }
-  }
-
-  property("Prefixing should work for verification ops") {
-    class Test extends Module {
-      val foo, bar = IO(Input(UInt(8.W)))
-
-      {
-        val x5 = {
-          val x1 = chisel3.assert(1.U === 1.U)
-          val x2 = cover(foo =/= bar)
-          val x3 = chisel3.assume(foo =/= 123.U)
-          val x4 = printf("foo = %d\n", foo)
-          x1
-        }
-      }
-    }
-    val chirrtl = ChiselStage.emitChirrtl(new Test)
-    (chirrtl should include).regex("assert.*: x5")
-    (chirrtl should include).regex("cover.*: x5_x2")
-    (chirrtl should include).regex("assume.*: x5_x3")
-    (chirrtl should include).regex("printf.*: x5_x4")
-  }
-
-  property("Leading '_' in val names should be ignored in prefixes") {
-    class Test extends Module {
-      {
-        val a = {
-          val _b = {
-            val c = Wire(UInt(3.W))
-            4.U // literal because there is no name
-          }
-          _b
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a_b_c"))
-    }
-  }
-
-  // This checks that we don't just blanket ignore leading _ in prefixes
-  property("User-specified prefixes with '_' should be respected") {
-    class Test extends Module {
-      {
-        val a = {
-          val _b = prefix("_b") {
-            val c = Wire(UInt(3.W))
-          }
-          4.U
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a__b_c"))
-    }
-  }
-
-  property("Leading '_' in signal names should be ignored in prefixes from connections") {
-    class Test extends Module {
-      {
-        val a = {
-          val b = {
-            val _c = IO(Output(UInt(3.W))) // port so not selected as wire
-            _c := {
-              val d = Wire(UInt(3.W))
-              d
-            }
-            4.U // literal so there is no name
-          }
-          b
-        }
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("a_b_c_d"))
-    }
-  }
-
-  property("Prefixing of AffectsChiselPrefix objects should work") {
-    class NotAData extends AffectsChiselPrefix {
-      val value = Wire(UInt(3.W))
-    }
-    class NotADataUnprefixed {
-      val value = Wire(UInt(3.W))
-    }
-    class Test extends Module {
-      {
-        val nonData = new NotAData
-        // Instance name of nonData.value should be nonData_value
-        nonData.value := RegNext(3.U)
-
-        val nonData2 = new NotADataUnprefixed
-        // Instance name of nonData2.value should be value
-        nonData2.value := RegNext(3.U)
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("nonData_value", "value"))
-    }
-  }
-  property("Prefixing should not be affected by repeated calls of suggestName") {
-    class Test extends Module {
-      val in = IO(Input(UInt(3.W)))
-      val prefixed = {
-        val wire = Wire(UInt(3.W)).suggestName("wire") // "prefixed_wire"
-        wire := in
-
-        val thisShouldNotBeHere = {
-          // Second suggestName doesn't modify the instanceName since it was
-          // already suggested, but also should not modify the prefix either
-
-          // Incorrect behavior would rename the wire to
-          // "prefixed_thisShouldNotBeHere_wire"
-          wire.suggestName("wire")
-
-          val out = IO(Output(UInt(3.W)))
-          out := wire
-          out
-        }
-        thisShouldNotBeHere
-      }
-    }
-    aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("prefixed_wire"))
-    }
-  }
-}
diff --git a/src/test/scala/chiselTests/naming/ReflectiveNamingSpec.scala b/src/test/scala/chiselTests/naming/ReflectiveNamingSpec.scala
deleted file mode 100644
index baa991dd..00000000
--- a/src/test/scala/chiselTests/naming/ReflectiveNamingSpec.scala
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.naming
-
-import chisel3._
-import chiselTests.{ChiselFlatSpec, Utils}
-
-class ReflectiveNamingSpec extends ChiselFlatSpec with Utils {
-
-  behavior.of("Reflective naming")
-
-  private def emitChirrtl(gen: => RawModule): String = {
-    // Annoyingly need to emit files to use CLI
-    val targetDir = createTestDirectory(this.getClass.getSimpleName).toString
-    val args = Array("--warn:reflective-naming", "-td", targetDir)
-    (new chisel3.stage.ChiselStage).emitChirrtl(gen, args)
-  }
-
-  it should "NOT warn when no names are changed" in {
-    class Example extends Module {
-      val foo, bar = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-
-      val sum = foo +& bar
-      out := sum
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should equal("")
-    chirrtl should include("node sum = add(foo, bar)")
-  }
-
-  it should "warn when changing the name of a node" in {
-    class Example extends Module {
-      val foo, bar = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-
-      val sum = foo +& bar
-      val fuzz = sum
-      out := sum
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should include("'sum' is renamed by reflection to 'fuzz'")
-    chirrtl should include("node fuzz = add(foo, bar)")
-  }
-
-  // This also checks correct prefix reversing
-  it should "warn when changing the name of a node with a prefix in the name" in {
-    class Example extends Module {
-      val foo, bar = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-
-      // This is sketch, don't do this
-      var fuzz = 0.U
-      out := {
-        val sum = {
-          val node = foo +& bar
-          fuzz = node
-          node +% 0.U
-        }
-        sum
-      }
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should include("'out_sum_node' is renamed by reflection to 'fuzz'")
-    chirrtl should include("node fuzz = add(foo, bar)")
-  }
-
-  it should "warn when changing the name of a Module instance" in {
-    import chisel3.util._
-    class Example extends Module {
-      val enq = IO(Flipped(Decoupled(UInt(8.W))))
-      val deq = IO(Decoupled(UInt(8.W)))
-
-      val q = Module(new Queue(UInt(8.W), 4))
-      q.io.enq <> enq
-      deq <> q.io.deq
-
-      val fuzz = q
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should include("'q' is renamed by reflection to 'fuzz'")
-    chirrtl should include("inst fuzz of Queue")
-  }
-
-  it should "warn when changing the name of an Instance" in {
-    import chisel3.experimental.hierarchy.{Definition, Instance}
-    import chiselTests.experimental.hierarchy.Examples.AddOne
-    class Example extends Module {
-      val defn = Definition(new AddOne)
-      val inst = Instance(defn)
-      val fuzz = inst
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should include("'inst' is renamed by reflection to 'fuzz'")
-    chirrtl should include("inst fuzz of AddOne")
-  }
-
-  it should "warn when changing the name of a Mem" in {
-    class Example extends Module {
-      val mem = SyncReadMem(8, UInt(8.W))
-
-      val fuzz = mem
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should include("'mem' is renamed by reflection to 'fuzz'")
-    chirrtl should include("smem fuzz")
-  }
-
-  it should "NOT warn when changing the name of a verification statement" in {
-    class Example extends Module {
-      val in = IO(Input(UInt(8.W)))
-      val z = chisel3.assert(in =/= 123.U)
-      val fuzz = z
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should equal("")
-    // But the name is actually changed
-    (chirrtl should include).regex("assert.*: fuzz")
-  }
-
-  it should "NOT warn when \"naming\" a literal" in {
-    class Example extends Module {
-      val out = IO(Output(UInt(8.W)))
-
-      val sum = 0.U
-      val fuzz = sum
-      out := sum
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should equal("")
-    chirrtl should include("out <= UInt")
-  }
-
-  it should "NOT warn when \"naming\" a field of an Aggregate" in {
-    class Example extends Module {
-      val io = IO(new Bundle {
-        val in = Input(UInt(8.W))
-        val out = Output(UInt(8.W))
-      })
-      val in = io.in
-      val out = io.out
-      out := in
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should equal("")
-    chirrtl should include("io.out <= io.in")
-  }
-
-  it should "NOT warn when \"naming\" unbound Data" in {
-    class Example extends Module {
-      val in = IO(Input(UInt(8.W)))
-      val out = IO(Output(UInt(8.W)))
-      val z = UInt(8.W)
-      val a = z
-      out := in
-    }
-    val (log, chirrtl) = grabLog(emitChirrtl(new Example))
-    log should equal("")
-    chirrtl should include("out <= in")
-  }
-}