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| author | Jack Koenig | 2021-12-07 13:18:29 -0800 |
|---|---|---|
| committer | GitHub | 2021-12-07 21:18:29 +0000 |
| commit | e85bfebb5d661de41f9ccac300fb48bf92840cfe (patch) | |
| tree | c0209789b1226ad7e3ad14921831dca65b340d1d /src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala | |
| parent | 12ed3fe9a780a9914b3f5727d921b4e419967549 (diff) | |
[docs] Remove body from minimizing output bits recipe (#2290)
Remove the body from the emitted Verilog. This was the original intent
of the example, and it avoids an issue where Jekyll was not able to
render the Markdown file due to Verilog concatenation looking like a
variable escape.
Diffstat (limited to 'src/test/scala/chiselTests/experimental/DataViewTargetSpec.scala')
0 files changed, 0 insertions, 0 deletions