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authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /src/test/scala/chiselTests/VecLiteralSpec.scala
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/VecLiteralSpec.scala')
-rw-r--r--src/test/scala/chiselTests/VecLiteralSpec.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index fa97a8c8..e2eb791d 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -205,7 +205,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
assertTesterPasses {
new BasicTester {
- chisel3.assert(outsideVecLit(0) === 0xdd.U, s"v(0)")
+ chisel3.assert(outsideVecLit(0) === 0xdd.U, "v(0)")
stop()
}
}
@@ -216,7 +216,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
assertTesterPasses {
new BasicTester {
- chisel3.assert(outsideVecLit(0) === 0xdd.U, s"v(0)")
+ chisel3.assert(outsideVecLit(0) === 0xdd.U, "v(0)")
chisel3.assert(outsideVecLit(1) === 0xcc.U)
chisel3.assert(outsideVecLit(2) === 0xbb.U)
chisel3.assert(outsideVecLit(3) === 0xaa.U)