Merge branch '3.5.x' into 3.5-release

1 files changed, 2 insertions, 3 deletions

diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index 228f409b..fa97a8c8 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -434,7 +434,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
     exc.getMessage should include("field 0 specified with non-literal value UInt")
   }
 
-  "vec literals are instantiated on connect" in {
+  "vec literals are instantiated on connect and are not bulk connected" in {
     class VecExample5 extends RawModule {
       val out = IO(Output(Vec(2, UInt(4.W))))
       val bundle = Vec(2, UInt(4.W)).Lit(
@@ -463,13 +463,12 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
     out := bundle
   }
 
-  "vec literals can contain bundles" in {
+  "vec literals can contain bundles and should not be bulk connected" in {
     val chirrtl = (new chisel3.stage.ChiselStage).emitChirrtl(new VecExample, args = Array("--full-stacktrace"))
     chirrtl should include("""out[0].bar <= UInt<5>("h16")""")
     chirrtl should include("""out[0].foo <= UInt<6>("h2a")""")
     chirrtl should include("""out[1].bar <= UInt<2>("h3")""")
     chirrtl should include("""out[1].foo <= UInt<3>("h7")""")
-
   }
 
   "vec literals can have bundle children" in {