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authorJim Lawson2015-11-06 14:40:30 -0800
committerJim Lawson2015-11-06 14:40:30 -0800
commit85f3006d7eac44ff21111d0f7ece1015164c0fe0 (patch)
tree60775f61ca8a481631ba67554a995ef1822b2ec0 /src/test/scala/chiselTests/Vec.scala
parent730c951f4271120931062df674a9cd1303d226ad (diff)
parent7fe61318433a8ecaac80ef2b547a88ab9dc04aec (diff)
Merge pull request #59 from ucb-bar/testing-improvements
Further testing improvements
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
-rw-r--r--src/test/scala/chiselTests/Vec.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 4430ab66..6d16ec08 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -29,7 +29,7 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
val (cnt, wrap) = Counter(Bool(true), n*2)
when(wrap) { io.done := Bool(true) }
- val shifter = Vec(Reg(UInt(width = log2Up(n))), n)
+ val shifter = Reg(Vec(UInt(width = log2Up(n)), n))
(shifter, shifter drop 1).zipped.foreach(_ := _)
shifter(n-1) := cnt
val expected = cnt - UInt(n)
@@ -48,7 +48,7 @@ class VecSpec extends ChiselPropSpec {
forAll(smallPosInts) { (n: Int) => assert(execute{ new TabulateTester(n) }) }
}
- property("Vecs of regs should be usable as shift registers") {
+ property("Regs of vecs should be usable as shift registers") {
forAll(smallPosInts) { (n: Int) => assert(execute{ new ShiftRegisterTester(n) }) }
}
}