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authorAndrew Waterman2016-02-04 00:00:19 -0800
committerAndrew Waterman2016-02-04 00:00:19 -0800
commit62fa95acc5d3d301fe461c5844c29d0c75ca6a5d (patch)
tree89893f19fba9aacc7e18ba8013b428e9f1e03482 /src/test/scala/chiselTests/Vec.scala
parent7fc2ea6a14da441db9c47d094361fea07436f6d3 (diff)
parentc5240a3bfe1c05a206c7c34c3c7c5007bbcc3680 (diff)
Merge branch 'blackbox't push origin master
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
-rw-r--r--src/test/scala/chiselTests/Vec.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 0c3d046e..f48c1b63 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -44,15 +44,15 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
class VecSpec extends ChiselPropSpec {
property("Vecs should be assignable") {
forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
- assert(execute{ new ValueTester(w, v) })
+ assertTesterPasses{ new ValueTester(w, v) }
}
}
property("Vecs should tabulate correctly") {
- forAll(smallPosInts) { (n: Int) => assert(execute{ new TabulateTester(n) }) }
+ forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new TabulateTester(n) } }
}
property("Regs of vecs should be usable as shift registers") {
- forAll(smallPosInts) { (n: Int) => assert(execute{ new ShiftRegisterTester(n) }) }
+ forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
}
}